Stacked
capacitor memory is realized, wherein a
capacitor stores data and a
diode serves as an access device instead of MOS
transistor, the first terminal is connected to a word line, the second terminal is connected to the first
electrode of the
capacitor which serves as a storage node while the second
electrode is connected to a plate line, the third terminal is floating, and the fourth terminal is connected to a
bit line. When write, the storage node is charged or not, depending on the conducting state of the
diode which is controlled by the
bit line. When read, the
diode also serves as a
sense amplifier to detect whether the storage node is forward bias or not, and it sends binary data to a latch device wherein includes a
current mirror and a
feedback loop which cuts off the current path after latching, thus it reduces active current, minimizes data pattern sensitivity, and also rejects
coupling noise. And dummy rows and columns generate replica
delay signals which guarantee
timing margin and reduce
cycle time. And its applications are extended to single port,
multi port and
content addressable memory. In addition, the memory cells are formed in between the routing
layers, which memory cells can be stacked over the
transistor or another capacitor
memory cell.