54results about How to "Increase capacitor area" patented technology

Provided are a low temperature active matrix display device using a plastic substrate and method of fabricating the same. The low temperature active matrix display device includes: a plastic substrate; a reflection layer disposed on the plastic substrate; a buffer layer disposed on the reflection layer; a thin film transistor disposed on the buffer layer in a first region of the plastic substrate; an interlayer dielectric layer disposed on the thin film transistor; a capacitor disposed in a trench formed in a second region of the plastic substrate and having a first electrode connected to a source electrode and a drain electrode of the thin film transistor, the trench extending from the interlayer dielectric layer to the reflection layer; and a display device having one electrode connected to a second electrode of the capacitor. The above-described structure includes photoresist spacers to decrease a leakage current from the TFT, includes a reflector to protect the plastic substrate from deformation due to laser irradiation, and employs a three-dimensional capacitor to increase an aperture ratio.

A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

A method for fabricating a deep trench capacitor for dynamic memory cells in which a trench is etched into the depth of a semiconductor substrate, and wherein the interior of the trench is provided with a doping and a dielectric and is filled with a conductive material as an inner electrode. The inner electrode and the dielectric are etched back within a collar region, and a collar is formed using a collar process comprising a collar oxide deposition and etching back of the collar oxide on the substrate surface and in the trench as far as the inner electrode, after which the inner electrode is completed by further steps of depositing and etching back conductive layers. Prior to the doping a masking layer is applied to the collar region of the trench, and this masking layer is removed again before the collar process. Before the dielectric is applied the surface of the lower regions of the trench outside the collar region a layer of grains of conductive material is applied.

An optical semiconductor device including: a substrate having a principal surface; a first and a second optical waveguides disposed on the principal surface of the substrate, the first and second optical waveguides extending in a first direction, the second optical waveguide being arranged adjacent to the first optical waveguide in a second direction intersecting with the first direction; a first and a second signal electrodes disposed on the first and second optical waveguides; a resistor disposed on the principal surface, the resistor being arranged between the first optical waveguide and the second optical waveguide, the resistor being electrically connected to the first signal electrode and the second signal electrode; a resin layer disposed on the principal surface, top surfaces of the first and second signal electrodes, and the resistor; and a capacitor disposed on the resin layer, the capacitor being electrically connected to the resistor through an opening of the resin layer.

The invention discloses a floating gate type EEPROM (Electrically Erasable Programmable Read Only Memory) device. A memory cell of the EEPROM device comprises a memory transistor and a selection transistor, wherein the memory transistor comprises a floating gate positioned at the lower part and a control gate positioned at the upper part; and a dielectric layer is arranged between the floating gate and the control gate, and is in a curved surface shape. The invention further discloses a manufacturing method of the device, which mainly comprises the step that the floating gate is subjected to shallow trench etching, so that the dielectric layer is in the concave curved surface shape. Compared with the traditional flat dielectric layer, the capacitance area is increased; and the increased capacitance is proportional to the depth of a shallow trench, so that the voltage coupling efficiency and the coupled voltage are increased, and the area of the existing device can be kept or even reduced.

A method of integrating the fabrication of a capacitor cell and a logic device region, wherein the surface area of a capacitor region is increased, and the risk of a capacitor depletion phenomena is reduced, has been developed. After formation of insulator filled STI regions featuring tapered sides, a portion of the insulator layer in an STI region is recessed below the top surface of the semiconductor substrate exposing a bare, tapered side of the semiconductor substrate. Ion implantation into the tapered side of the portion of semiconductor substrate exposed in the recessed STI portion, as well as into a top portion of semiconductor substrate located adjacent to the recessed STI portion, results in formation of a capacitor region now greater in surface area than a counterpart capacitor region which is formed via implantation into only a top portion of semiconductor substrate. Growth of a gate insulator layer and definition of gate structures in the logic device region, also simultaneously forms a capacitor dielectric layer on the underlying capacitor region, as well as a capacitor plate structure in the capacitor cell region.

A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

An optical-to-electrical converter unit includes a substrate having front and back surfaces; an optical waveguide unit; and an optical-to-electrical converter. The optical-to-electrical converter includes a light-receiving element optically coupled to the optical waveguide unit; a capacitance element including first and second conductive layers and an insulating layer disposed between the first and second conducive layers; an electrode pad electrically connected to the light-receiving element; a back electrode formed on the back surface of the substrate; and a via electrode extending from the front surface to the back surface of the substrate. The optical waveguide unit, the light-receiving element, the capacitance element, and the electrode pad are formed on the front surface. The first conductive layer of the capacitance element is electrically connected to the light-receiving element and the electrode pad. The second conductive layer of the capacitance element is electrically connected to the back electrode through the via electrode.

A method of integrating the fabrication of a capacitor cell and a logic device region, wherein the surface area of a capacitor region is increased, and the risk of a capacitor depletion phenomena is reduced, has been developed. After formation of insulator filled STI regions featuring tapered sides, a portion of the insulator layer in an STI region is recessed below the top surface of the semiconductor substrate exposing a bare, tapered side of the semiconductor substrate. Ion implantation into the tapered side of the portion of semiconductor substrate exposed in the recessed STI portion, as well as into a top portion of semiconductor substrate located adjacent to the recessed STI portion, results in formation of a capacitor region now greater in surface area than a counterpart capacitor region which is formed via implantation into only a top portion of semiconductor substrate. Growth of a gate insulator layer and definition of gate structures in the logic device region, also simultaneously forms a capacitor dielectric layer on the underlying capacitor region, as well as a capacitor plate structure in the capacitor cell region.

A thin film transistor substrate according to an exemplary embodiment includes: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the gate electrode; an oxide semiconductor disposed on the gate insulating layer; a first interlayer insulating layer disposed on the oxide semiconductor; a data line disposed on the first interlayer insulating layer; a second interlayer insulating layer disposed on the data line; a source electrode disposed on the second interlayer insulating layer and connected with the oxide semiconductor and the data line through a first contact hole through the second interlayer insulating layer; and a drain electrode disposed on the second interlayer insulating layer and connected with the semiconductor through a second contact hole through the second interlayer insulating layer.

A method of fabricating a deep trench is provided, by which a trench is formed in the substrate initially. Then, a block layer is formed on the substrate surface of the upper portion of the trench. After that, a pad oxide layer is formed on the substrate surface of the lower portion of the trench. Next, a plurality of hemispherical silicon grains is formed on the substrate and exposes a portion of the pad oxide layer. Then, by using the hemispherical silicon grains as a mask, a portion of the pad oxide layer is removed so as to form a patterned pad oxide layer. Continually, the hemispherical silicon grains and the substrate exposed by the patterned pad oxide layer are removed. Finally, the patterned pad oxide layer is removed.

The invention relates to a pressure sensing module and a touch display substrate provided with the pressure sensing module. The pressure sensing module comprises a base, an elastic layer, a first electrode layer, a piezoelectric material layer and a second electrode layer, wherein the base, the elastic layer and the first electrode layer are sequentially arranged in a stacked mode; the elastic layer comprises multiple micro-structures which form a concavo-convex surface; the first electrode layer, the piezoelectric material layer and the second electrode layer cooperate to form a pressure sensing module body; and the pressure sensing module body is arranged on the elastic layer and used for sensing pressure exerted on the pressure sensing module.

The invention discloses a method for improving metal-insulator-metal (MIM) capacitor reliability. The method comprises the following steps of sequentially depositing a first metal dielectric layer, a metal layer, a corrosion stopping layer and a second metal dielectric layer on a substrate; forming a first through hole and a second through hole in the second metal dielectric layer and covering a bottom anti-reflex layer on the surface of the second metal dielectric layer; manufacturing a multilayer groove on the second through hole and forming a laminated groove with gradually-increased bottom width; manufacturing the bottom portion of the multilayer groove into a first chamfer, enabling the first through hole to be contacted with the second metal dielectric layer, and manufacturing a connection position between the top end and the multilayer groove into a second chamfer; and etching the first through hole and the second through hole to the surface of the first metal dielectric layer and sequentially forming a top electrode, an insulating film and a bottom electrode on the surface of the second metal dielectric layer from top to bottom. The invention further discloses a process structure of the method for improving the metal-insulator-metal MIM capacitor reliability. The method and the process structure can improve reliability of MIM capacitor devices.

In a semiconductor device producing method, a plug is formed within a contact hole formed in a barrier film and an interlayer insulating film on a semiconductor substrate. Then, an insulation film is formed on the plug and barrier film, and a hole is made in the insulation film such that an upper surface of the plug is exposed. A first conductive film is formed on the insulation film so as to fill the hole, and then etched by a CMP method to form a lower electrode within the hole. The insulation film is removed and the lower electrode is left in a protuberant manner. A dielectric film made of a ferroelectric or high-dielectric-constant substance and a second conductive film are sequentially formed over the lower electrode and the barrier film, and then patterned simultaneously to thereby form a capacitor dielectric film and an upper electrode.

The invention relates to a substrate, which contains an oxide silicon layer, a first nitride silicon layer, a shallow channel isolate, and the second nitride silicon layer. It forms a designed multicrystalline layer on the second nitride silicon layer, and etches the designed multicrystalline layer to form the deep ditch shedding, and then it removes the multicrystalline layer and simultaneously etches the substrate to deepen the deep channel shedding by etching method and to fill a capacitor structure into the deep channel.

An LC composite component comprising an element body, a helically wound coil disposed in the element body, and a capacitor disposed on an outer circumferential side of the coil in the element body. When viewed in an axial direction of the coil, the element body is rectangular, and the capacitor is disposed between at least two sides of the element body and the coil.

Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. Surfaces of the cup-shaped lower electrode and the top supporting layer are covered by the capacitor dielectric layer. A surface of the capacitor dielectric layer is covered by the upper electrode.

Phase-locked loop circuitry includes charge pump circuitry, loop filter circuitry, and drag current circuitry. The charge pump circuitry generates a charge pump current based on a phase of an input signal. The loop filter circuitry receives the charge pump current. The drag current circuitry generates a drag current to draw charge in the opposite direction from the charging current from a loop filter integration capacitor in the loop filter circuitry that does not include voltage sensing circuitry.

An electronic device includes a power converter and a current detector that is disposed at at least one position out of a primary-side position and a secondary-side position for the power converter and detects a current flowing at the at least one position. A snubber circuit including a capacitor is directly connected in parallel to both ends of the current detector.

The invention discloses a back capacitor structure and a manufacturing method. The method comprises the following steps of arranging a nitride layer on the front of a semiconductor substrate and arranging a hole, directly facing the nitride layer, in the back of the semiconductor substrate, wherein the nitride layer is arranged at the bottom of the hole; arranging first metal layers on the inner wall of the hole and the back of the semiconductor substrate; arranging dielectric layers on the inner wall of the hole and the back of the semiconductor substrate, wherein the dielectric layers coverthe first metal layers; arranging through holes in the dielectric layer above the first metal layers of the semiconductor substrate; and manufacturing a hole in the back of the semiconductor substrate. The capacitor structure in the manufactured hole is capable of greatly improving the capacity area, thereby improving the area utilization rate of an epitaxy structure; the occupied planar space issmaller, so that benefit is provided to reduce the device size; and the back capacitor is manufactured without changing the original manufacturing process, so that the process cost is saved.

The invention provides a preparation method of a three-dimensional ferroelectric random access memory and the three-dimensional ferroelectric random access memory. The preparation method comprises thefollowing steps: while preparing a transistor based on a CMOS process, vertically integrating each ferroelectric storage unit of a three-dimensional ferroelectric capacitor on the transistor in sequence to obtain the three-dimensional ferroelectric random access memory. The ferroelectric storage unit of the three-dimensional ferroelectric capacitor sequentially comprises an interlayer medium (7),a capacitor bottom electrode (9), a ferroelectric film (10) and a capacitor top electrode (11) which are vertically deposited. A ferroelectric capacitor is integrated into a complementary metal oxidesemiconductor (CMOS), and a capacitor structure is converted from a plane to a three-dimensional structure to increase a capacitor area, so that higher storage density is realized, and the size of astorage unit is further reduced on the premise of not reducing storage charges.

The invention discloses a microchip capacitor and a manufacturing method thereof. The chip capacitor comprises a prefabricated solder tin layer, a prefabricated solder gold layer, a barrier layer, analuminum-silicon alloy substrate, a bonding layer, a conductive layer, a dielectric layer and an electrode layer which are stacked in sequence. The manufacturing method comprises the following steps:S1, providing an aluminum-silicon alloy substrate and carrying out pretreatment; S2, preparing a barrier layer on the first surface of the aluminum-silicon alloy substrate, and preparing a bonding layer on the second surface of the aluminum-silicon alloy substrate; S3, plating gold on the barrier layer to form a prefabricated solder gold layer, and plating a conductive layer on the bonding layer;S4, sputtering a dielectric layer and an electrode layer on the conductive layer; S5, forming a prefabricated solder tin layer on the prefabricated solder gold layer through tin electro-deposition; and S6, scribing to obtain the independent microchip capacitor. According to the invention, the aluminum-silicon alloy is used as the substrate, the substrate does not need to be polished or sputtered with a priming coat, the capacitor area is large, the manufacturing period is short, and the assembling difficulty of the microchip capacitor is reduced.

Phase-locked loop circuitry includes charge pump circuitry, loop filter circuitry, and drag current circuitry. The charge pump circuitry generates a charge pump current based on a phase of an input signal. The loop filter circuitry receives the charge pump current. The drag current circuitry generates a drag current to draw charge in the opposite direction from the charging current from a loop filter integration capacitor in the loop filter circuitry that does not include voltage sensing circuitry.

An optical-to-electrical converter unit includes a substrate having front and back surfaces; an original waveguide unit; and an optical-to-electrical converter. The optical-to-electrical converter includes a light-receiving element optically coupled to the optical waveguide unit; a capacitance element including first and second conductive layers and an insulating layer disposed between the first and second conductive layers; an electrode pad electrically connected to the light-receiving element; a back electrode formed on the back surface of the substrate; and a via electrode extending from the front surface to the back surface of the substrate. The optical waveguide unit, the light-receiving element, the capacitance element, and the electrode pad are formed on the front surface. The first conductive layer of the capacitance element is electrically connected to the light-receiving element and the electrode pad. The second conductive layer of the capacitance element is electrically connected to the back electrode through the via electrode.