32results about How to "Reduce Capacitance Variation" patented technology

Wirings mainly containing copper are formed on an insulating film on a substrate. Then, after forming insulating films for reservoir pattern and a barrier insulating film, an insulating film for suppressing or preventing diffusion of copper is formed on upper and side surfaces of the wirings, the insulating film on the substrate, and the barrier insulating film. Here, thickness of the insulating film for suppressing or preventing diffusion of copper at the bottom of a narrow inter-wiring space is made smaller than that on the wirings, thereby efficiently reducing wiring capacitance of narrow-line pitches. Then, first and second low dielectric constant insulating films are formed. Here, a deposition rate of the first insulating film at an upper portion of the side surfaces of facing wirings is made higher than that at a lower portion thereof, thereby forming air gaps. Finally, the second insulating film is planarized by interlayer CMP.

A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.

An electro-optical device is provided with a plurality of data lines, a plurality of potential lines supplied with a predetermined potential, a driving transistor controlling a current level according to the voltage between the gate and the source, a first storage capacitor which holds the voltage between the gate and a source of the driving transistor, and a light-emitting element. One data line among the plurality of data lines and one potential line among the plurality of potential lines are arranged to be adjacent to each other, and a second storage capacitor holding the potential of the one data line is formed by the one data line and the one potential line.

A sensor for determining the presence of an analyte is disclosed comprising a reactive layer disposed between a base plate and a movable plate. The reactive layer is configured to interact with an analyte effecting a change in capacitance between the base plate and movable plate. When the analyte has a polarity or overall Hildebrand solubility parameter that is similar to the reactive layer, the change in capacitance is caused by a swelling of the reactive layer as analyte is absorbed into the reactive layer. This results in a decrease in capacitance. When the analyte has a solubility parameter not near the reactive layer, the absorbed analyte causes the reactive layer's total polarity to increase, an effect that dominates swelling. This causes an increase in capacitance. A capacitive sensing circuit is included for measuring the change in capacitance which is indicative of the analyte exposed to the sensor.

The invention discloses a display and an electronic unit. The display device includes a display element, a transistor configured to drive the display element, the transistor including a channel region, and a retention capacitor. An oxide semiconductor film is provided in areas across the transistor and the retention capacitor, the oxide semiconductor film including a first region formed in the channel region of the transistor, and a second region having a lower resistance than that of the first region. The second region is formed in the areas of the transistor and retention capacitor other than in the channel region.

Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in poor RC time constants of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated or substantially reduced by selectively providing an etch-resistant masking material at thinner, i.e., recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second and third dielectric layers deposited over the planarized surface. The second and third dielectric layers are selected such that the second dielectric layer etches at a substantially slower rate than the third dielectric layer, thereby serving as a partial etch stop layer preventing deleterious over-etching of the borderless via.

A display panel includes a plurality of scan lines, a plurality of data lines, a plurality of power lines, a plurality of light emitting units, a plurality of first pixel circuits and a plurality of second pixel circuits. The plurality of light emitting units are arranged in an array and adapted to display different colors. In the organic light emitting units with the same color, some parts are connected to the first pixel circuits, and other parts are connected to the second pixel circuits. A first terminal and a second terminal of a first control transistor in the first pixel circuit are sequentially arranged on a forward direction of a first direction, and a first terminal and a second terminal of a second control transistor in the second pixel circuit are sequentially arranged on a reverse direction of the first direction.

The invention discloses a flexible sensor capable of simultaneously detecting pressure-strain dual-mode signals and a preparation method. The sensor comprises a lower packaging protection layer, a lower electrode plate, first metal lead layers, a porous dielectric layer, second metal lead layers, an upper electrode plate and an upper packaging protection layer. The lower electrode plate and the upper electrode plate are made of low-dimensional nano materials, when the device is prepared, the low-dimensional nano material of the lower electrode plates are diffused towards the upper surface of the lower packaging protection layer to form a first diffusion layer, and the low-dimensional nano materials of the upper electrode plate are diffused towards the upper surface of the porous dielectric layer to form a second diffusion layer; the lower electrode plate and the upper electrode plate serve as electrode plate parts of the capacitor structure and are used for sensing pressure signals, and serve as strain gauge structures and are used for sensing stretching signals. The preparation method of the sensor is simple, two ends of the low-dimensional nano material are embedded into the upper and lower elastomers, so that the upper and lower layers form effective connection, and later additional assembly and adhesion are not needed.

A capacitor structure implemented as a layered structure including a plurality of alternating dielectric and metallization layers, and a method of manufacturing such capacitor structure. The capacitor structure including at least one lateral parallel plate capacitor part (LPP part) including two first electrodes on two different layers separated by dielectric material of a plurality of the alternating layers, and at least one vertical parallel plate capacitor part (VPP part) including two second electrodes each including a plurality of superimposed slabs or bars arranged on a plurality of the metallization layers. The at least one LPP part is electrically coupled with the at least one VPP part to form the capacitor structure. A variation in capacitance value of the at least one LPP part due to a variation of thickness of dielectric material is at least partially compensated by an opposite variation in capacitance value of the at least one VPP part.