41results about How to "Potential fluctuation" patented technology

A liquid crystal panel (2) includes scanning signal lines (31) for supplying scanning signals to gate electrodes (20) of TFTs (14), and data signal lines (32) for supplying data signals to data electrodes (24) of TFTs. The liquid crystal panel further includes auxiliary capacitive electrode pads (27a) for use in forming auxiliary capacitance and an auxiliary capacitive lines (33) so as not to generate a capacitive bond with the scanning signal lines. The liquid crystal panel is driven at a rewriting frequency of a screen of not more than 30 Hz. As a result, the liquid crystal panel can be driven at a low consumption power while maintaining a desirable display quality of the liquid crystal panel.

The invention relates to a semiconductor component with trench isolation and to an associated fabrication method, a trench isolation (STI, TTI) having a deep isolation trench with a covering insulation layer (10, 11), a side wall insulation layer (6) and an electrically conductive filling layer (7), which is electrically connected to a predetermined doping region (1) of the semiconductor substrate in a bottom region of the trench. The use of a trench contact (DTC), which has a deep contact trench with a side wall insulation layer (6) and an electrically conductive filling layer (7), which is likewise electrically connected to the predetermined doping region (1) of the semiconductor substrate in a bottom region of the contact trench, makes it possible to improve the electrical shielding properties with a reduced area requirement.

In a display driver, one scanning period is divided into a period P and a subsequent period D. In the period P, a pre-charge voltage equal to an original data voltage is applied in a time-sharing manner to data lines in one block, and in the period D after the period P, the original data voltage is applied again.

There is provided an LSI socket containing a pogo-pin type decoupling capacitor for reducing the potential fluctuation of power supplies and GNDs at the time of testing LSI incorporated in a BGA package. The LSI socket comprises a printed board 102 containing decoupling capacitors 113 corresponding to one or more power supply voltages inside thereof, a pogo-pin supporting casing portion 104 on which the printed board 102 is overlapped into a single piece, and pogo-pins 103 inserted into penetrating holes in which hole positions of through holes 109 drilled in the printed board 102 and casing holes 114 drilled in the pogo-pin supporting casing portion 104 are allowed to be matched, wherein the printed board 102 is disposed on the upper surface side of the pogo-pin supporting casing portion 104 which faces the BGA package, or disposed on the lower surface side of the pogo-pin supporting casing portion 104, at the time of testing the LSI incorporated in the BGA package.

A pixel circuit 10 is provided with TFTs 12 and 13 and an organic EL element 15 on a current path connecting a power supply line VPk and an electrode having a common potential Vcom. A display device 100 simultaneously performs initialization to pixel circuits 10 in a plurality of rows, simultaneously perform threshold detection to the pixel circuits 10 in the plurality of rows, sequentially writes data to the pixel circuits 10 row by row, and makes the organic EL elements 15 included in the pixel circuits 10 in the plurality of rows emit light in the same period. In a period from completion of threshold detection to start of light emission, the TFTs 11 and 13 are controlled to an off state, and a potential VP_C which is substantially equal to the common potential Vcom is applied to the power supply line VPk. Consequently, leak current flowing through the TFTs 12 and 13 can be suppressed, and the fluctuation in the node potential in the pixel circuit 10 in a standby period can be prevented.

In a display driver, one scanning period is divided into a period P and a subsequent period D. In the period P, a pre-charge voltage equal to an original data voltage is applied in a time-sharing manner to data lines in one block, and in the period D after the period P, the original data voltage is applied again.

An electro-optical device includes a plurality of data lines, a plurality of scanning lines, a plurality of unit circuits that are provided in correspondence with intersections of the data lines and the scanning lines. Each of the data lines is supplied with a data voltage in accordance with a gray-scale level. Each of the scanning lines is supplied with a scanning signal that specifies a writing period during which the data voltage is being written into the corresponding unit circuits. Each of the plurality of unit circuits includes a driving transistor, an electro-optical element, a capacitive element, a power feed line, a first switching element and a second switching element. The driving transistor generates a driving current in accordance with an electric potential of a gate thereof. The electro-optical element generates light with a gray-scale level in accordance with the driving current that is generated by the driving transistor. The capacitive element has a first electrode and a second electrode that is connected to the gate of the driving transistor. The power feed line is supplied with a constant electric potential and is, during an initialization period that is different from the writing period, electrically connected to the second electrode. The first switching element conducts the gate of the transistor with the drain thereof at least during the initialization period. The second switching element switches between conduction and non-conduction between the data line and the first electrode on the basis of the scanning signal. The power feed line is arranged in a direction that intersects with the scanning lines.

An image display device includes a display element having a unit of display comprising sub pixels displaying images for first and second view points, respectively, and an optical unit that distributes lights emitted from respective sub pixels into different directions. When a region surrounded by a data line, a gate line and a storage capacitor electrode in the sub pixel is defined as an aperture, the sub pixels form a base unit that is an adjoining pixel pair including two sub pixels arranged via a data line therebetween. The two sub pixels have switching elements connected to the data line between the two sub pixels and controlled by different gate lines. When virtual lines each evenly dividing a width of the sub pixel in the first direction into K+1 pieces are presumed, K number of storage capacitor lines are each arranged across at least one virtual line in the aperture.

A memory operable at a high speed is obtained. This memory comprises a plurality of word lines, first transistors each connected to each the plurality of word lines for entering an ON-state through selection of the corresponding word line, a plurality of memory cells including diodes having cathodes connected to the source or drain regions of the first transistors respectively and a data determination portion connected to the drain or source regions of the first transistors for determining data read from a selected memory cell.