81 results about "Dram cache" patented technology

The present invention provides a non-volatile flash memory management system and method that provides the ability to efficiently manage a large array of flash devices and allocate flash memory use in a way that improves reliability and longevity, while maintaining excellent performance. The invention mainly comprises of a processor, an array of flash memories that are modularly organized, an array of module flash controllers and DRAM caching. The processor manages the above mention large array of flash devices with caching memory through mainly two tables: Virtual Zone Table and Physical Zone Table, a number of queues: Cache Line Queue, Evict Queue, Erase Queue, Free Block Queue, and a number of lists: Spare Block List and Bad Block List.

The invention provides a DRAM (dynamic random access memory)-NVM (non-volatile memory) hierarchical heterogeneous memory system adopting software and hardware collaborative management. According to the system, an NVM is taken as a large-capacity NVM for use while DRAM is taken as a cache of the NVM. Hardware overhead of a hierarchical heterogeneous memory architecture in traditional hardware management is eliminated through effective use of certain reserved bits in a TLB (translation lookaside buffer) and a page table structure, a cache management problem of the heterogeneous memory system is transferred to the software hierarchy, and meanwhile, the memory access delay after missing of final-stage cache is reduced. In view of the problems that many applications in a big data application environment have poorer data locality and cache pollution can be aggravated with adoption of a traditional demand-based data prefetching strategy in the DRAM cache, a Utility-Based data prefetching mechanism is adopted in the DRAM-NVM hierarchical heterogeneous memory system, whether data in the NVM are cached into the DRAM is determined according to the current memory pressure and memory access characteristics of the applications, so that the use efficiency of the DRAM cache and the use efficiency of the bandwidth from the NVM main memory to the DRAM cache are increased.

The invention relates to a novel USB protocol computer accelerating device based on the multi-channel SLC NAND and the DRAM cache memory. The novel USB protocol computer accelerating device comprises a main control chip and an SLCNAND module and is provided with a USB interface connected with a computer. Cache files, a cache system and regularly-used files of application programs are established for the computer and distributed in the SLCNAND and a DRAM and scattered files which are frequently read and written are used as high-speed cache. Meanwhile, a device driver improves a USB protocol. A BOT protocol in a traditional USB interface protocol is optimized and resource distribution and optimization is performed on a USB transport protocol. The algorithm and the frame of the device adopt the design which includes that firstly, virtualization is carried out on application programs by the device, and therefore, all program files and system environment files needed by the programs are pre-stored in the device; secondly, a multi-channel mode is adopted, and an array module integrates multiple SLCNANA chips and adopts multi-channel main control; thirdly, data to be used are judged by the system by monitoring habits of users for a long time and pre-stored in the device; fourthly, intelligent compressing and backstage automatic releasing are performed on system memory.

A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.