139 results about "Dynamic memory management" patented technology

An architecture for a contactless smart card or payment device, where the smart card is intended for use in both commerce transaction payment and transit fare payment (or other venue access) environments. The payment device may function as both an electronic wallet for commerce transactions and as a transit system card, for access to and fare payment of transit services. Implementation of both functions may be achieved by use of a dynamic memory management system that permits data for both the payment and transit applications to be stored on the card, with the transit data and storage locations isolated from those used to store data intended for use in paying for commerce transactions. The transit application specific data may include access control data (keys, passwords, identification data) or data required for fare calculations (rates, historical data on system use), for example.

An architecture for a contactless smart card or payment device, where the smart card is intended for use in both commerce transaction payment and transit fare payment (or other venue access) environments. The payment device may function as both an electronic wallet for commerce transactions and as a transit system card, for access to and fare payment of transit services. Implementation of both functions may be achieved by use of a dynamic memory management system that permits data for both the payment and transit applications to be stored on the card, with the transit data and storage locations isolated from those used to store data intended for use in paying for commerce transactions. The transit application specific data may include access control data (keys, passwords, identification data) or data required for fare calculations (rates, historical data on system use), for example.

Method, system, and computer program product embodiments for facilitating data transfer from a write cache and NVS via a device adapter to a pool of storage devices by a processor or processors are provided. The processor(s) adaptively varies the destage rate based on the current occupancy of the NVS for a particular storage device and stage activity related to that storage device. The stage activity includes one or more of the storage device stage activity, device adapter stage activity, device adapter utilized bandwidth and the read / write speed of the storage device. These factors are generally associated with read response time in the event of a cache miss and not ordinarily associated with dynamic management of the destage rate. This combination maintains the desired overall occupancy of the NVS while improving response time performance.

The invention disclosed a multi-thread processor dynamic memory management system and method. The system includes a message treament module, a main control memory management module and a memory monitoring module. The method includes the steps: a main kernel thread applies to one-stage memory as a memory pool from the memory of system; all kernel threads tranmit the message for applying to the memory for main kernal thread, and main kernel thread distributes free memory in the memory pool to the kernel thread for applying to the memory after receiving the message for applying to the memory, and transmits the message for distributing the memory for the kernel thread for applying to the memory; main control kernel thread inquires the use of memory which has been applied by the kernel thread, and transmits the message of callbacking memory; the kernel thread returns the memory after receiving the medssage of callbacking memory, and transmits the message of releasing the memory for main control thread. The use of memory in the system ia able to be improved using the inventive multi-thread processor dynamic memory management system and method.

An embodiment of this invention pertains to a system and method for balancing memory accesses to a low cost memory unit in order to sustain and guarantee a desired line rate regardless of the incoming traffic pattern. The memory unit may include, for example, a group of dynamic random access memory units. The memory unit is divided into memory channels and each of the memory channels is further divided into memory lines, each of the memory lines includes one or more buffers that correspond to the memory channels. The determination as to which of one or more buffers within a memory line an incoming information element is stored is based on factors such as the number of buffers pending to be read within each of the memory channels, the number of buffers pending to be written within each of the memory channels, and the number of buffers within each of the memory channels that has data written to it and is waiting to be read.

A first processor and a second processor are configured to communicate secure inter-processor communications (IPCs) with each other. The first processor effects secure IPCs and non-secure IPCs using a first memory management unit (MMU) to route the secure and non-secure IPCs via a memory system. The first MMU accesses a first page table stored in the memory system to route the secure IPCs and accesses a second page table stored in the memory system to route the non-secure IPCs. The second processor effects at least secure IPCs using a second MMU to route the secure IPCs via the memory system. The second MMU accesses the second page table to route the secure IPCs.

A number of improvements in network adapters that offload protocol processing from the host processor are provided. Specifically, mechanisms for handling memory management and optimization within a system utilizing an offload network adapter are provided. The memory management mechanism permits both buffered sending and receiving of data as well as zero-copy sending and receiving of data. In addition, the memory management mechanism permits grouping of DMA buffers that can be shared among specified connections based on any number of attributes. The memory management mechanism further permits partial send and receive buffer operation, delaying of DMA requests so that they may be communicated to the host system in bulk, and expedited transfer of data to the host system.

The invention discloses a dynamic memory management system based on memory hot plug for a virtual machine, comprising a memory monitoring module, a memory distributing module and a memory hot plug module. The memory hot plug module adopts Linux memory hot plug mechanism to realize memory hot plug on a semi-virtual Linux virtual machine, thereby breaking through the initial memory toplimit of the virtual machine and efficiently improving the memory expandability of the virtual machine by increasing and reducing the memory randomly. On one hand, the memory distributing module dynamically predicts the memory requirement of the virtual machine and balances the memory pressure of each virtual machine, thereby being capable of satisfying the memory requirement of the virtual machine and also improving the memory utilization ratio of a physical machine; on the other hand, the memory distributing module can establish a new virtual machine by reasonably reducing the memory of the existing virtual machine when the memory of the physical machine is not enough, thereby realizing memory overuse and improving the memory utilization ratio of the physical machine.

With better knowledge of the behavior of objects in a running application, it is possible to improve execution environment decisions that affect management of such objects. For example, if available, object lifetime statistics could be employed in decisions that affect how and where objects are placed, e.g., on allocation or during operation of automatic dynamic memory management facilities such as a garbage collector. Typically, instrumenting all objects to sample lifetimes or other characteristics would impose an impractical level of overhead. We present a technique for dynamic sampling of a subset of allocated objects that incurs low runtime overheads. Coupled with automatic memory management or collection facilities, this technique allows us to improve the efficiency of a collector by segregating objects, sampled and non-sampled alike, based on observed characteristics such as object lifetime. The sampling techniques facilitate tracking of many kinds of object information. For purposes of illustration, an exemplary implementation is described in which such sampling techniques are exploited to improve performance of generational garbage collectors.

A method and system for secure dynamic memory management using heap memory, or analogous dynamic memory allocation, that includes initializing a heap memory segment, having a plurality of buffers, within a random access memory. When an allocation request to store data in the heap memory segment is received, one of the buffers is randomly selected. Metadata, containing details of allocated and unallocated buffers of the heap memory segment, is then maintained in a portion of the memory separate from the heap object. According to certain embodiments, the secure heap of the present disclosure can securely implement the functions of those portions of the C / C++ stdlib library related to dynamic memory management, specifically malloc ( ) free ( ) and their variants.

A method, system, and program for dynamic memory management of unallocated memory in a logical partitioned data processing system. A logical partitioned data processing system typically includes multiple memory units, processors, I / O adapters, and other resources enabled for allocation to multiple logical partitions. A partition manager operating within the data processing system manages allocation of the resources to each logical partition. In particular, the partition manager manages allocation of a first portion of the multiple memory units to at least one logical partition. In addition, the partition manager manages a memory pool of unallocated memory from among the multiple memory units. Responsive to receiving a request for a memory loan from one of the allocated logical partitions, a second selection of memory units from the memory pool is loaned to the requesting logical partition. The partition manager, however, is enabled to reclaim the loaned selection of memory units from the requesting logical partition at any time.

A dynamic memory management method and apparatus wherein an area of a memory is partitioned into a plurality of areas to form memory banks. The different priority classes share the memory banks. A policer (write controller) dynamically assigns input frame data of a plurality of classes having different degrees of priority to memory banks in accordance with the degrees of priority and stores the data there for each priority class. A scheduler (read controller) sequentially reads out the data from the frame data stored in the memory bank assigned to the class having the highest degree of priority and transmits the same. For storage of frame data of a priority of class input in a burst like manner, a plurality of memory banks are assigned to that priority class so as to raise the burst tolerance. By controlling writing and reading of data in units of memory banks, the control can be simplified. Due to this, the efficiency of usage of memory is improved and the write / read control is simplified.

The embodiments of the invention provide a memory leak positioning method and electronic equipment, and relate to the technical field of memory management. Unified application and release interface functions of a memory unit are monitored by using a Hook technology without modifying a system memory management module, so that a block memory and a page memory with memory leak are accurately positioned. The method comprises the steps of: when the memory unit is applied via an application interface function, saving a mapping relation between the memory unit and an identifier of a function call stack, wherein the function call stack saves a function call relation of the memory unit applied via the application interface function, and the memory unit comprises block memories or page memories; when the memory unit is released via a release interface function, clearing the mapping relation between the memory unit and the identifier of the function call stack corresponding to the memory unit; and according to the multiple statistical memory sizes of the memory unit having the mapping relation with the identifier of each function call stack, determining the function call stack and the function with memory leak. The method is used for positioning memory leak.