Memory system cache mechanism based on flash memory

Abstract

The invention relates to a memory system cache mechanism based on flash memory. It is provided that two cache areas are constructed in the DRAM of the memory system based on the flash memory, namely a page cache area and a cache line cache area. On one hand, hot cache line in each data page is identified and stored through a history perception hotspot identification mechanism, and the hit rate of DRAM cache is increased. On the other hand, a delay refresh mechanism is adopted, and a clean data block is preferably removed when the cache area is full so as to reduce writing for the flash memory. Meanwhile, a weak variable coefficient algorithm is adopted, modes of history visit records, dirty mark bits and the like are added, and the expenses of the cache mechanism on time and space are not high. The memory system cache mechanism based on the flash memory utilizes the nature of the flash memory, writing delay of the memory system can be effectively improved, and service life of the memory system can be effectively prolonged.

Description

technical field [0001] The present invention is applicable to the technical field of memory systems based on flash memory, and provides a memory system cache mechanism based on flash memory. Through the design of the cache, the load bottleneck when data accesses flash memory is alleviated, and the read-write delay and the delay of reading and writing of the memory system based on flash memory are improved. service life. Background technique [0002] With the rapid development of the information technology revolution, big data and cloud computing have become the mainstream of today's era. The explosive growth of data and the continuous improvement of computer performance have put forward higher and higher requirements for storage systems. Storage systems are facing capacity and performance challenge. [0003] The integration of traditional memory DRAM is getting higher and higher, and its capacity is getting bigger and bigger. Although its access delay has not been significa...

AI Technical Summary

Problems solved by technology

However, there are two key issues with this system: performance and longevity

However, if we use a simple caching mechanism to cache pages in flash memory into DRAM, traditional cache replacement algorithms, such as LRU (Least Recently Used), can only identify hot pages and save them in cache, and cannot identify Output the hot cache line in each page

Second, the existing general-purpose cache replacement mechanism only focuses on higher request hit ratios, and does not take into account the relevant characteristics of flash memory

The page size of the flash memory is inconsistent with the size of the cache line, so that the DRAM cache cannot identify the hot cache line in each page

At the same time, the traditional general-purpose cache replacement algorithm is not fully suitable for flash memory systems, and simply using it may reduce the performance and lifespan of the overall system

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