194results about How to "Improve erase efficiency" patented technology

A memory structure includes a substrate layer having opposite first and second surfaces, a conductive region formed therein, a top portion of the conductive region facing a first surface of the substrate layer and a bottom portion of the conductive region facing a second surface of the substrate layer, and a bottom portion of the conductive region facing a second surface of the substrate layer. Astorage layer located on a first surface of the substrate layer; An isolation structure penetrating through the substrate layer and located at the edge of the conductive region, and arranged around the conductive region for isolating the conductive region from the substrate layer of the periphery of the isolation structure; The conductive region includes a shield layer located at the bottom of theconductive region and a P-type doped well located above the shield layer. The performance of the memory is improved.

The present invention relates to a flash memory unit structure with a high coupling ratio and a preparation method thereof. The flash memory unit structure comprises: a semiconductor substrate, wherein the semiconductor substrate comprises two shallow trench isolations and an active area, and the active area is located in the semiconductor substrate between the two shallow trench isolations; a tunneling oxide layer; a floating gate; a dielectric layer; and a control gate, wherein the dimensions of the top portions of the two shallow trench isolations are equal to the dimension of the top portion of the active area, and the dimension of the tunneling oxide layer is equal to the dimension of the top portion of the active area. A silicon nitride reduction resistance amount prior to depositionof the shallow trench isolations is increased to increase the dimensions of the top portions of the shallow trench isolations; and moreover, in the subsequent technology process, the top portions ofthe shallow trench isolations can be consumed, the dimensions of the top portions of the shallow trench isolations after consumption are equal to the actual dimension of the top portion of the activearea to allow the width of the bottom portion of the floating gate to be equal to the dimension of the top portion of the active layer when a subsequent floating gate process is performed so as to reduce the capacitance of the floating gate to the substrate and increase the coupling ratio of a flash unit.

The invention discloses a partial erasing liquid-crystal handwriting board device and a forming method thereof. The partial erasing liquid-crystal handwriting board device comprises a liquid-crystal handwriting board and an erasing pen. The liquid-crystal handwriting board includes a substrate, a first conductive layer, an infrared absorbing material layer, a liquid crystal layer, a second conductive layer, and a flexible transparent substrate. The first conductive layer and the infrared absorbing material layer are arranged on the substrate in a basic dimension consistence manner. The first conductive layer and the second conductive layer are transparent conductive layers; the second conductive layer is formed on the flexible transparent substrate; and the substrate and the flexible transparent substrate jointly clamp the liquid crystal layer to form a liquid crystal box of the liquid-crystal handwriting board. The erasing pen includes an infrared emitting light source and a control switch. According to the partial erasing liquid-crystal handwriting board device, the partial erasing is realized by means of non-contact photothermal conversion; the erasing efficiency is high; the device is convenient to use; and energy-saving and low-cost effects are realized.

The invention provides a method for manufacturing a flash memory device. When a sidewall of a gate stack layer is formed, a first protective layer is formed on a side wall of the sidewall; and the protective layer and the sidewall are etching-selective in a process of removing the sidewall in a word line region; in this way, when the sidewall in the word line region is removed, the protective layer can protect the sidewall of an erase gate region from being removed, and the sidewall of the erase gate region is a mask when a floating gate is formed. The protective layer can reduce or avoid damage to the mask forming the floating gate, thereby improving the uniformity of the formed floating gate, improving the erasing efficiency of the flash memory device and improving the performance of theflash memory device.

A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage to a source line of at least one memory block selected from among the plurality of memory blocks during an erase operation, a read and write circuit suitable for applying an initial setting voltage, to bit lines of at least one memory block during the erase operation, and a control logic suitable for controlling the voltage generator and the read and write circuit to apply the initial setting voltage to the bit lines before applying the erase voltage to the source line.

The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

The invention discloses an erasing method of a flash memory device and a flash memory device. The flash memory device comprises a plurality of blocks, each of which is composed of a plurality of memory cells, wherein the memory cells are the smallest data storage units of the flash memory device; a controller, configured to receive a write instruction carrying an erase parameter from an external main controller, and write the erase parameter into a register, and to receive an erase instruction for a target block from an external master controller and obtain an erase parameter of the target block, determine an erase voltage corresponding to the target block based on an erase parameter of the target block, and perform an erase operation on the target block based on the determined erase voltage; and a register which is used for storing the erase parameter.