Formation method for split gate storage device

Abstract

The invention discloses a formation method for a split gate storage device, which is composed of a semiconductor substrate, wherein the semiconductor substrate is successively provided with a gate dielectric layer, a floating gate polycrystalline silicon layer and a hard mask layer. The formation method comprises the following steps: performing trench isolation etching on the hard mask layer, floating gate polycrystalline silicon layer, gate dielectric layer and part of the semiconductor substrate to form isolated trenches; filling dielectric in the isolated trenches; and removing the hard mask layer. By adopting the self-alignment shallow slot isolation method to form the floating gate polycrystalline silicon layer, the thickness uniformity of the floating gate polycrystalline silicon layer is improved and the consistency of the erasing performance of storage units can be ensured.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a method for forming a discrete gate storage device. Background technique [0002] With the development of the semiconductor industry, due to the wide application of memory devices, their output accounts for a considerable proportion of integrated circuit products. Among storage devices, the development of flash memory (flash memory for short) is particularly rapid in recent years. The main feature of flash memory is that it can keep stored information for a long time without power on; and it has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Therefore, flash memory has been widely used in many fields such as computers and automation control. widely used. [0003] The standard physical structure of flash memory is called a memory cell (bit). The structure of flash memory is different from that of conventional MOS transistors. Usu...

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Problems solved by technology

[0013] The above solution uses CMP to planarize the polysilicon material layer 222 to form a polysilicon layer with a floating gate structure. The thickness uniformity of the polysilicon layer with a floating gate structure obtained by using CMP at different positions on the substrate 200 is relatively poor. The resulting floating gate structure differs in thickness between different memory cells by up to The electrical properties of the final formed memory cells are quite different

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