A 3D memory device and a data operation method thereof

Abstract

The invention discloses a data operation method of a 3D storage device. The 3D memory device has a plurality of memory cell strings arranged in a direction perpendicular to a substrate, each memory cell string including a first select transistor, a first dummy memory cell, a plurality of main memory cells, a second dummy memory cell, and a second select transistor, including: receiving an erase instruction; executing an erase operation on the first pseudo storage unit, the plurality of main storage units and the second pseudo storage unit according to the erase instruction; verifying whether the plurality of main storage units are erased successfully or not after the erase operation is finished; when the plurality of main storage units are erased successfully, receiving a programming instruction; and executing programming operation on the first pseudo storage unit and the second pseudo storage unit according to the programming instruction. The pseudo storage unit and the storage unit are erased at the same time, and then the pseudo storage unit is programmed, so that the erasure efficiency of the edge storage unit is improved, the erasure frequency is reduced, and the reliability of the storage unit is improved.

Description

technical field [0001] The present invention relates to memory technology, and more specifically, to a 3D memory device and a data operation method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] Such as Figure 1a and 1b As shown, the three-dimensional memory of the vertical channel structure includes a plurality of memory cell strings 100 arranged in a direction perpe...

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Problems solved by technology

[0006] However, in the erasing process, for the edge memory cells adjacent to the dummy memory cells, since the first dummy memory cell and the second dummy memory cell are floating, it will affect the erasing electric field of the edge memory cells, reducing the edge storage capacity. Cell Erase Efficiency

In order to make the threshold voltage of the edge memory cell reach the preset value, more erasing times are required, which increases the erasing time

On the other hand, due to the increase in the number of erasures, it will be erased deeper for other memory cells, resulting in a decrease in the reliability of the three-dimensional memory

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