74results about How to "Reduce erasure time" patented technology

A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.

The invention discloses an erasing method for a non-volatile memory. The method comprises the following steps of: selecting a target, namely, selecting 2n to-be-erased adjacent memory blocks in the non-volatile memory, wherein n is a natural number; performing pre-programming operation, namely, pre-programming the 2n adjacent memory blocks in groups; erasing, namely, simultaneously erasing the 2n adjacent memory blocks; checking the erasing, namely, checking whether the 2n adjacent memory blocks are successfully erased in groups, if so, performing soft programming operation, and otherwise, returning to the erasing step; and performing the soft programming operation, namely, performing the soft programming operation on the adjacent memory blocks in groups. The method can save erasing time and improve erasing speed and erasing efficiency.

A data writing method and a memory controller and a memory storage apparatus using the same are provided. The data writing method includes grouping a plurality of physical blocks into a plurality of physical units, grouping the physical units into at least a data area and a free area, and configuring a plurality of logical units for mapping to the physical units of the data area. The data writing method also includes getting a physical unit from the free area, writing data in at least one of the logical units into the gotten physical unit, and writing an end mark into the gotten physical unit, and in the gotten physical unit, the end mark follows the data belonging to the at least one logical unit. Thereby, the storage space of each physical unit can be effectively used, and the lifespan of the memory storage apparatus can be prolonged.

The invention discloses a software and hardware combined nonvolatile memory erasure control method capable of prolonging the service life. The method comprises the steps that first, a software is configured with and uses the multi-pulse erasure and enables the enhanced reading; then, the system initiates a request for erasing a nonvolatile memory, the hardware suspends the CPU clock, and the execution of other instructions is prevented; and after the erasing process is completed, the hardware reads the data of the erasing block by using a more strict standard, judges whether the erasing is successful, and informs the software of an erasing result flag bit; if the erase is successful, the CPU clock is turned on, and the subsequent instruction operation is executed continuously; if the erasefails, the software initiates a second erase instruction operation until the correct data is read; if the continuous N times of multi-pulse erase fails, the (N + 1)-th software enables the normal reading, and the data of the erase block is read; if the continuous N times of multi-pulse erase is successful, it is considered that the erase succeeds, otherwise, the erase process fails, wherein N canbe preset. According to the present invention, the service life of the nonvolatile memory can be effectively prolonged.

A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block.

A data storage system including a processor configured to execute a plurality of tasks, wherein the processor is configured to generate writing status information based on the data relevant information and otre the data relevant information and the writing status information in association with each other in the nonvolatile memory when the processor write data in the recording medium based on demand of the task and writing to the recording medium is configured to be controlled based on the data relevant information and the write-in status information stored in nonvolatile memory.

The invention discloses a method and a system for reducing erasing interference and erasing time, a storage medium and a terminal. The method comprises the step of performing first refreshing processing on other programming units which belong to the same array as an erased unit in a chip by adopting a sampling inspection mode or performing first refreshing processing on other programming units which belong to the same array as the erased unit in the chip by adopting a circulating mode. Although certain reliability of the chip is sacrificed, the erasing time is greatly reduced, and the use requirements of products are met.