330results about How to "High-speed performance" patented technology

A thin-film transistor including an oxide semiconductor layer is disclosed. The oxide semiconductor layer includes a first area, a second area and a third area forming a well-type potential in the film-thickness direction. The first area forms a well of the well-type potential and has a first electron affinity. The second area is disposed nearer to the gate electrode than the first area and has a second electron affinity smaller than the first electron affinity. The third area is disposed farther from the gate electrode than the first area and has a third electron affinity smaller than the first electron affinity. At least an oxygen concentration at the third area is lower than an oxygen concentration at the first area.

A nonvolatile storage device is provided with a nonvolatile main storage memory whose erase size is larger than a cluster size, and a buffer, i.e. a nonvolatile auxiliary storage memory. At the time of writing data in the memory, the data is temporarily stored in the buffer, then, a plurality of data in the buffer are collectively taken out to be stored in the main storage memory. Data in an original block is saved in a write block in the main storage memory. Thus, the data can be written in the main storage memory at a high speed.

A BGA semiconductor device for high-speed operation and high pin counts has a base which is constituted by a core layer formed of wiring boards and surface layers provided on both sides of the core layer, and a semiconductor element mounted on the base. Through holes in a signal region of the core layer are disposed in an optimum through hole pattern in which power through holes and ground through holes are disposed adjacent to signal through holes.

A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off.

A visible light communication apparatus is constituted with a transmitter for illuminating and projecting visible light on which an information signal is superimposed from a lamp fitting and a receiver for receiving the visible light to take out the information signal superimposed on the visible light. The transmitter modulates a transmission information signal, driving a light projecting element of the lamp fitting so as to superimpose the transmission information signal on the visible light of the lamp fitting, thereby radiating white light containing a blue light component as visible illumination light. The receiver receives the white visible light containing the blue light component radiated from the transmitter and generates a receiving information signal from the light receiving signal on a receiving circuit. A blue light photodiode which receives blue light at the highest sensitivity to output a light receiving signal is used as a light receiving element of the light receiving unit. The lamp fitting for radiating the white light containing the blue light component on the side of the transmitter as visible illumination light and the blue light photodiode for receiving blue light on the side of the receiver at the highest sensitivity can be used to perform visible light communications at high speed, while illuminating by the white light.

A nonvolatile semiconductor memory device includes a readout circuit which reads data stored in a selected memory cell by applying predetermined voltage to the selected memory cell and a reference cell such that currents corresponding to the respective threshold voltage may flow, and comparing the current flowing in the selected memory cell with the current flowing in the reference cell. The readout circuit commonly uses the reference cell set in the same storage state for normal readout and for readout for program verification, and when the predetermined voltage is applied to the selected memory cell and the reference memory cell at the time of the readout for the program verification, it sets an applying condition to the reference memory cell such that its storage state may be shifted more in the program state direction than that in an applying condition at the time of the normal readout.