69results about How to "Avoid overetching" patented technology

A display substrate includes a metal pattern, a first insulation layer pattern and a second insulation layer pattern. The metal pattern is on a base substrate. The first insulation pattern is on the metal pattern and includes one of a silicon nitride (SiN_x) and a silicon oxide (SiO_x). The second insulation pattern is on the first insulation pattern and includes a remaining one of the silicon nitride (SiN_x) and the silicon oxide (SiO_x).

A semiconductor device comprises a substrate having contact pads each covered by under bump metallurgy and a plurality of bump electrodes respectively provided on the under bump metallurgy covering the contact pads. According to one embodiment of the present invention, the semiconductor device is characterized by having at least one contact pad (e.g., a test contact pad) which is not provided with any bump electrode but still has under bump metallurgy provided thereon. According to another embodiment of the present invention, the semiconductor device is characterized by having at least a conductive line formed of the same material as the under bump metallurgy for interconnecting at least two of the contact pads. The present invention further provides methods of manufacturing the semiconductor devices.

A method of manufacturing a semiconductor device having an isolation region, a trench formed on a semiconductor substrate and an insulating film buried within the trench; includes: forming a gate electrode in an active region adjacent to the isolation region; applying an ion implantation onto the substrate to form a first dopant diffusion region; forming a first and a second insulating film, on the entire surface of the substrate; performing an etch back, to form a first sidewall of the second insulating film on a lateral face of the gate electrode; etching the first insulating film to form a second sidewall of the first insulating film on the lateral face of; making another ion implantation to form a second dopant diffusion region; forming an interlayer insulating film; and forming a contact hole to reach the second dopant diffusion region.

A polarizing device includes: a polarizing device unit composed of a metallic film formed on a base, the metallic film having a plurality of slit-shaped openings; and an etching sacrifice layer provided between the base and the polarizing device unit, so that the etching sacrifice layer is partly etched together with the metallic film during the etching of the polarizing device unit; wherein the etching sacrifice layer is composed of a material that has an etching rate equal to or greater than that of the metallic film.

A method of manufacturing the semiconductor device is provided, which provides a prevention for a “dug” of a silicon substrate caused by the etching in regions except a region for forming a film during a removal of the film with a chemical solution. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first silicon oxide film on a surface of a silicon substrate or on a surface of a gate electrode when a silicon nitride film for a dummy side wall is etched off, to provide a protection for such surfaces, and then etching a portion of the silicon nitride film with a chemical solution, and then a second oxide film for supplementing a simultaneously-etched portion of the first silicon oxide film is formed, and eventually performing an etching for completely removing the silicon nitride film for the dummy side wall.

A method of fabricating a flash memory device, having a double gate structure, including an oxide/nitride/oxide (ONO) layer, provides more stable operation by using a dummy pattern upon forming the ONO layer and using a control gate after forming a floating gate. The method includes steps of forming a floating gate on a semiconductor substrate; forming a dummy pattern on the floating gate; etching the floating gate using the dummy pattern as a hard mask; forming an insulating layer flush with an upper surface of the dummy pattern; removing the dummy pattern to leave a space for an ONO layer and control gate formation; and sequentially forming an ONO layer and a control gate in the space left by removing the dummy pattern.

A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate, containing first doping ions and including a pixel region for forming a pixel structure; forming a deeply doped region, in the photosensitive region of the substrate and containing second doping ions; forming a floating diffusion area in the floating diffusion region of the substrate and containing third doping ions; forming a gate structure on the substrate at the junction of the photosensitive region and the floating diffusion region; forming a sidewall film covering the gate structure and the substrate; forming a sidewall spacer; forming a first doped region in the floating diffusion region on one side of the gate structure; forming a metal connection layer on the first doped region; forming an interlayer dielectric layer on the substrate; and forming a source/drain contact plug in the interlayer dielectric layer.

Disclosed is a manufacturing method to fabricate Heterojunction Bipolar Transistors (HBTs) that enables self-alignment of emitter and base metal contact layers with precise sub-micron spacing using a dielectric-assisted metal lift-off process. Such an HBT process relies on the formation of an “H-shaped” dielectric (i.e., Si₃N₄/SiO₂) mask conformally deposited on top of the emitter contact metallization that is used to remove excess base metal through lift-off by a wet chemical HF-based etch. This HBT process also uses a thin selective etch-stop layer buried within the emitter layer to prevent wet chemical over-etching to the base and improves HBT reliability by forming a non-conducting, depleted ledge above the extrinsic base layer. The geometry of the self-aligned emitter and base metal contacts in the HBT insures conformal coverage of dielectric encapsulation films, preferably Si₃N₄ and/or SiO₂, for reliable HBT emitter p-n junction passivation. Thus, the disclosed HBT process enables scaling of narrow emitter stripe widths down to sub-micron dimensions producing transistors with cut-off frequencies in the range of several hundred GigaHertz.

A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse.

A semiconductor device manufacturing method includes: forming a first isolation region for setting a high-voltage-proof transistor forming region in a semiconductor layer; forming a second isolation region for setting a low-voltage-driven transistor forming region in the semiconductor layer by shallow-trench-isolation processing; and forming an offset insulating layer for electric field relaxation of high-voltage-proof transistors in the semiconductor layer by local-oxidation-of-silicon processing. The second step including: forming a trench in the semiconductor layer; forming an insulating layer filling up the trench and covering the entire upper surface of the semiconductor layer; removing part of the exposed insulating layer with a mask covering the insulating layer above a the offset insulating layer forming region and the trench forming region; removing at least the insulating layer in the high-voltage-proof transistor forming region by chemical-mechanical-polishing; and removing the insulating layer in the offset insulating layer forming region.

An integrated circuit structure includes a fuse. The integrated circuit structure further includes a first dielectric layer and a patterned dummy. The fuse is disposed on a substrate. The first dielectric layer covers the fuse. The patterned dummy is disposed on the first dielectric layer and the patterned dummy has a first recess exposing a part of the first dielectric layer directly above the fuse. A method of forming the integrated circuit structure including a fuse is also provided.

In a contact structure having a large aspect ratio in a LSI device incorporating DRAM cells and logics, for the purpose of preventing over-etching of a device isolation insulating film and an impurity diffusion layer and thereby minimizing junction leakage, a first etching stopper layer covering a peripheral MOS transistor and a second etching stopper layer overlying a capacitor section of a DRAM memory cell are formed. An impurity diffusion layer of the peripheral MOS transistor is connected to a metal wiring layer formed in an upper level of the capacitor section by an electrode layer extending through the first and second etching stopper layers. At least one of such impurity diffusion layers is connected to the electrode layer at its boundary with the device isolation insulating film, and depth of the bottom of the electrode layer formed on the device isolation insulating film from the surface of the impurity diffusion layer is shorter than the junction depth of the impurity diffusion layer.

A method of fabricating a MOS transistor, and the MOS transistor fabricated by the method, includes providing a substrate, forming a predetermined layer having a non-planar surface on the substrate, the predetermined layer including at least one active region, forming a gate electrode material layer on the non-planar, predetermined layer, forming a material layer and a hard mask layer on an entire surface of the gate electrode material layer, and planarizing a top surface of the material layer to form a planarized material layer, forming a photoresist pattern on the planarized material layer and the hard mask layer to pattern the gate electrode material layer, forming a hard mask pattern by etching the hard mask layer using the photoresist pattern as an etching mask, and forming a predetermined pattern by etching the planarized material layer and the gate electrode material layer according to a shape of the hard mask pattern.

A thin film transistor liquid crystal display (TFT-LCD) and fabrication method thereof. The fabrication method includes depositing a first metal layer on a transparent substrate, patterning the first metal layer to form at least two adjacent gate electrodes, forming a gate insulating layer on the gate electrodes, forming a semiconductor layer on the insulating layer, patterning the semiconductor layer into a predetermined shape, depositing a second metal layer on the transparent substrate, patterning the second metal layer to form a source/drain electrode layer, and depositing an insulating layer on the transparent substrate. A contact hole is defined via the insulating layer, source/drain electrode layer, and gate insulating layer, exposing a part of the surface of transparent substrate between the adjacent gate electrodes. A transparent conductive layer is deposited on the transparent substrate, and a light-shielding matrix is formed directly above the contact hole.

An internal filter includes a lower substrate and an upper substrate. Fluid passages are formed by etching grooves into the surface(s) of the upper and/or lower substrates, and/or in one or more intermediate layers. The filter pores extending between the fluid passages are formed by etching second grooves that fluidly connect the fluid passages. Two or more sets of the one or two intermediate layers can be implemented to provide additional filter passages and/or pores. Each set can be connected to a separate fluid source and/or a separate microfluidic device. In another internal filter, the inlet and outlet passages and the filter pores are formed on the same upper or lower substrate. The inlet and outlet passages are partially formed in a first step. In a second step, the inlet and outlet passages are completed at the same time that the filter pores are formed.