86 results about "Switched capacitor integrator" patented technology

A temperature to digital converter device is implemented by integrating a temperature sensor circuit into an analog-to-digital converter (ADC). Temperature-to-digital conversion is accomplished by first measuring a change in voltage (ΔVBE) across the junction of a diode when different current densities are forced through the junction. The thus obtained ΔVBE is proportional to temperature. As part of the conversion processing, ΔVBE is multiplied by a fixed gain, and an offset voltage value is subtracted from ΔVBE. The multiplication and subtraction functions are performed by a switched-capacitor integrator in a delta-sigma ADC and the ADC itself operates as the temperature-to-digital converter device, eliminating the extra amplifier and / or capacitors required when the multiplication and / or subtraction function are performed outside the ADC. Alternately, other ADC topologies that include an integrator or gain amplifier, such as pipeline ADCs and cyclic ADCs may be used in place of the delta-sigma ADC.

A single-ended or differential single-stage, or multi-stage sigma-delta analog-to-digital converter includes at least one switched-capacitor integrator comprising a switched-capacitor network receiving as input a signal to be sampled, and an amplifier coupled in cascade to the switched-capacitor network. A circuit is coupled to the amplifier for feeding an analog dither signal to a virtual ground of the amplifier.

Provided is a delta-sigma modulator having a differential output, the modulator including a switched-capacitor integrator configured to generate a non-inverted integral signal and an inverted integral signal and also including a switched-capacitor circuit configured to sample an input signal based on a control signal and to integrate the feedback signal and the input signal based on the control signal and also a feedback circuit configured to generate the feedback signal.

The invention discloses a digital-analog combined control body-bias class-C inverter, which comprises a main body class-C inverter module, a P-channel metal-oxide semiconductor (PMOS) body modulation module and an N-channel metal-oxide semiconductor (NMOS) body modulation module, wherein the PMOS body modulation module and the NMOS body modulation module can more precisely control parameters suchas a threshold voltage, a drain-source current, transconductance and the like of a first PMOS tube and a first NMOS tube in the main body class-C inverter module through links such as parameter sensing - current comparison - numeric counting - analog conversion - substrate bias voltage production and feedback and the like, so unfavorable influence of process deviation, power supply voltage disturbance and temperature variation on the main body class-C inverter module can be greatly reduced. The digital-analog combined control body-bias class-C inverter is applicable to the application fields requiring ultra-low power consumption and high precision such as switch capacitance integrating device, a sigma-delta analog-digital converter and the like.

The invention provides a complementation common-source common-grid inverter and an increment Sigma-Delta analog-to-digital conversion circuit. The increment Sigma-Delta analog-to-digital conversion circuit is composed of a second-order sigma delta modulator (101), a reduction sampling filter (102), a clock signal generation circuit (103) and a low-to-high voltage converter (104). A switch capacitance integrator at the band reset end of the second-order sigma delta modulator (101) comprises the complementation common-source common-grid inverter. The complementation common-source common-grid inverter comprises a first PMOS1 tube and a first NMOS1 tube. A second NMOS2 tube and a second PMOS2 tube are connected in series between the first PMOS1 tube and the first NMOS1, the second NMOS2 tube is arranged at an upper position, the grid end of the second NMOS2 tube is connected with a power supply voltage VDD, the second PMOS2 tube is disposed at a lower position, and the grid end of the second PMOS2 tube is grounded GND. The ADC provided by the invention has quite low power consumption and can work under the condition of low power supply voltage, thereby being applied to such fields of a portable instrument, measuring, and the like.

A switched capacitor integrator system includes an input cascoded amplifier circuit; a summing junction; an integrating switched capacitor circuit connected to the output of the input cascoded amplifier circuit and to the summing junction; the integrating switched capacitor circuit including an input switched capacitor circuit responsive to an input and connected to the summing junction; and a correlated double sampling capacitor circuit including an offset capacitor interconnected between the summing junction and the input of the input cascoded amplifier circuit.

A system for measuring a voltage drop between two nodes in an electrical circuit, comprising a switched capacitor integrator (SCI), a comparator and a counter. The SCI alternately (a) captures charge onto a set of sampling capacitors and (b) selectively accumulates / transfers the charge onto a pair of integration capacitors, where the charge includes a first portion that is based on the voltage drop and a second portion that depends on a digital indicator signal. The comparator generates the digital indicator signal based on whether an analog output of the SCI is positive or negative. The counter counts a number of ones occurring in the digital indicator signal during a measurement interval. At the end of the measurement interval, the count value represents a measure of the voltage drop. Knowing the resistance between the two nodes, the voltage drop may be converted into a current measurement.