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Digital-analog combined control body-bias class-C inverter

A kind of inverter-like, digital-analog hybrid technology, applied in the direction of logic circuits with logic functions, etc., can solve the problems of bulk modulation potential error, inability to achieve optimal compensation, process and temperature sensitivity, etc.

Inactive Publication Date: 2012-03-28
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the problem with the above-mentioned gain bootstrap type C-type inverter is that both the PMOS bulk potential modulation module and the NMOS bulk potential modulation module use resistors for current-voltage conversion, and the converted voltage is the final bulk modulation potential, while In the actual integrated circuit manufacturing, the resistance itself is more sensitive to the process and temperature, resulting in a certain error in the volume modulation potential generated by it, so the gain bootstrap C-type inverter cannot compensate for the process, power supply voltage and temperature. achieve the best results

Method used

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  • Digital-analog combined control body-bias class-C inverter
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  • Digital-analog combined control body-bias class-C inverter

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Embodiment Construction

[0030] The present invention will be described in detail below in conjunction with the embodiments and accompanying drawings, but the present invention is not limited thereto.

[0031] A digital-analog hybrid control body bias type C-type inverter, its circuit structure diagram is attached image 3 As shown, it includes a body class C inverter module 31 , a PMOS volume modulation module 32 and an NMOS volume modulation module 33 .

[0032]The main body type C inverter module 31 is composed of a first PMOS transistor M1, a first NMOS transistor M2, a second PMOS transistor M3 and a second NMOS transistor M4; wherein, the gate terminal of the first PMOS transistor M1 is connected to the first NMOS transistor M2 connected to the gate terminal of the main C-type inverter module 31 as the input terminal IN of the main C-type inverter module 31; the drain terminal of the second PMOS transistor M3 is connected to the drain terminal of the second NMOS transistor M4 as the output termi...

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Abstract

The invention discloses a digital-analog combined control body-bias class-C inverter, which comprises a main body class-C inverter module, a P-channel metal-oxide semiconductor (PMOS) body modulation module and an N-channel metal-oxide semiconductor (NMOS) body modulation module, wherein the PMOS body modulation module and the NMOS body modulation module can more precisely control parameters suchas a threshold voltage, a drain-source current, transconductance and the like of a first PMOS tube and a first NMOS tube in the main body class-C inverter module through links such as parameter sensing - current comparison - numeric counting - analog conversion - substrate bias voltage production and feedback and the like, so unfavorable influence of process deviation, power supply voltage disturbance and temperature variation on the main body class-C inverter module can be greatly reduced. The digital-analog combined control body-bias class-C inverter is applicable to the application fields requiring ultra-low power consumption and high precision such as switch capacitance integrating device, a sigma-delta analog-digital converter and the like.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a class C inverter. Background technique [0002] It is a new low-voltage low-power circuit design technique to replace the traditional operational amplifier with a class-C inverter. The most basic circuit structure in a class C inverter includes a PMOS (P-Channel Metal Oxide Semiconductor, P-channel Metal Oxide Semiconductor) input transistor and an NMOS (N-Channel Metal Oxide Semiconductor, N-channel Metal Oxide Semiconductor) input tube, the Class C inverter supply voltage V DD Slightly lower than the sum of the threshold voltages of the PMOS input tube and the NMOS input tube. Assuming that the threshold voltages of the PMOS input transistor and the NMOS input transistor are approximately equal, when the input signal is a common-mode voltage V CM =V DD / 2, the PMOS input tube and the NMOS input tube are both in the sub-threshold region. At this tim...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/20
Inventor 罗豪韩雁张泽松梁国廖璐虞春英
Owner ZHEJIANG UNIV
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