More ASIC functionality is crammed into a
chip (or
chip set) than can probably or definitely be operative at one time when the
chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different
market development probabilities in a host of different market spaces (e.g., in different countries where different
interoperability standards are chosen) and a subset of the excessive ASIC functionality is programmably activated in each market space after manufacture. Customer behavior can be fickle. If market trends evolve towards demand for functionality #2 instead of an originally, more expected, functionality #1, the
mass produced of the crammed chip (or chip set) is not out of necessarily out of luck. If the
mass produced had enough foresight to cram in functionality #2 as well as functionality #1, the producer can programmably activate #2, and deactivate #1 as market demand suddenly shifts in a given market space. In one embodiment, a
mega-ASIC with excessive ASIC functionality crammed into it, has a universal core as well as plurality of programmably selectable ASIC function blocks. The ASIC function blocks are programmably activatable and de-activatable so that a
mass produced can quickly respond to shifting market demands, thus addresses both
time to market and product life issues. The invention allows a small chip designer to simultaneously address more than one market or customer space with one ASIC chip thereby reducing the design cost per
product design. By selectively activating the excessive and selectable ASIC functionalities, the small ASIC chip designer can appear to sport different features for different customers and different markets at different times with just one chip, thus he can aggregate the demand of different customers and different markets to achieve economies of scale, and of
inventory management and control.