43 results about "Bipolar process" patented technology

The present invention provides a long time constant integrator circuit as part of an integrated circuit. The integrator circuit is fully integrated on chip with no external capacitive or resistive components for enhancing the circuit's time constant. It achieves a -3 dB cut-off frequency of 1.6 Hz. The circuit is realisable on a very small area of silicon being formed by a bipolar process using npn transistors, resistive and capacitive elements. The integrator circuit comprises a transconductance stage as an input to an operational amplifier. The circuit design is fully differential and employs realisable resistors and capacitors.

An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source / drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

Communication to or from a nanodevice is provided with a nanostructure-based antenna, preferably formed from, but not limited to, a single wall nanotube (SWNT). Other nanostructure-based antennas include double walled nanotubes, semiconducting nanowires, metal nanowires and the like. The use of a nanostructure-based antenna eliminates the need to provide a physical communicative connection to the nanodevice, while at the same time allowing communication between the nanodevice and other nanodevices or outside systems, i.e., systems larger than nanoscale such as those formed from semiconductor fabrication processes such as CMOS, GaAs, bipolar processes and the like.

An EEPROM memory cell uses silicon-germanium / silicon and emitter polysilicon film for fabricating shallow source / drain regions to increase a breakdown voltage with respect to a well. The source / drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

An EEPROM memory cell uses silicon-germanium / silicon and emitter polysilicon film for fabricating shallow source / drain regions to increase a breakdown voltage with respect to a well. The source / drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source / drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

An EEPROM memory cell uses silicon-germanium / silicon and emitter polysilicon film for fabricating shallow source / drain regions to increase a breakdown voltage with respect to a well. The source / drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

A power supply device 1 includes a control IC 3 fabricated by a bipolar process and a power supply element 4 fabricated by a MOS process, and has them die-bonded on a leadframe 2, with a chip edge of one of them kept in intimate contact with a chip edge of the other. Thus, heat conducts via those chip edges with increased efficiency, permitting the heat generated in the power supply element 4 to quickly conduct to the control IC 3. This prevents heat-induced breakdown to which a MOS semiconductor is susceptible. The power supply element 4 fabricated by a MOS process does not need to have a vertical structure as a bipolar PNP transistor does, and can a horizontal structure so that a current flows from one part of the top surface of the chip to another. This makes it easy to reduce power loss. Thus, the power supply element 4 and the control IC 3 can be connected, at the bottom surfaces of their chips, to a common GND potential, and can thus be together die-bonded with a single type of die-bonding paste as exemplified by Ag paste 5. This prevents electrostatic breakdown to which a bipolar semiconductor is susceptible.

The invention discloses a power integration module for an air conditioner and a manufacturing method of the power integration module. The power integration module comprises a substrate; a first to third upper bridge arm switch tubes and a first to third lower bridge arm switch tubes, which are all arranged on the substrate; a first to three high and low voltage drive tubes which are disposed on the substrate and are used for respectively driving the first to third upper and lower bridge arm switch tubes to operate, wherein the first high-voltage driving tube, the second high-voltage driving tube and the third high-voltage driving tube are achieved through the BCD or SOI process of the first voltage, and the first, second and third low-voltage driving tubes are achieved through the BCD or Bipolar process of the second voltage. The power integration module is configured on the corresponding switching tubes through the independent high-voltage driving tubes and low-voltage driving tubes,so as to enable the paths from the high-voltage driving tubes and low-voltage driving tubes to the grid electrodes of the corresponding switching tubes to be consistent, thereby guaranteeing the consistency of the dynamic characteristics of the switching tubes effectively, greatly saving the area of circuit wiring, greatly reducing the area of a circuit substrate of the intelligent power module, and reducing the cost.

The invention provides a single-power-supply, low-power-consumption and rail-to-rail input and output operational amplifier based on a bipolar process, which belongs to the technical field of analog integrated circuits and particularly comprises a biasing circuit, an input stage, a gain stage, an output stage and a frequency compensation network. The bias circuit adopts a bipolar peak current source to provide microampere bias current; the input stage adopts a complementary differential pair structure to realize rail-to-rail common-mode input, and realizes constant transconductance of the input stage by using a cross conduction method; wherein the gain stage and the input stage form a folding cascode structure, and a signal from the input stage passes through the source follower to serve as an input signal of a gain stage differential pair; the output stage adopts AB type rail-to-rail output so as to provide expansible output current sink (sinking current) and output current source (sourcing current) capabilities; the frequency compensation network provides sufficient phase margin for the operational amplifier, and stable unit gain bandwidth is realized.

In a complementary SiGe bipolar process, a pnpn thyristor structure is formed from some of the layers of a pnp transistor and an npn transistor formed on top of each other and making use of the SiGe gates to define the blocking junction.

A power supply device includes a control IC fabricated by a bipolar process and a power supply element fabricated by a MOS process, both of them die-bonded on a leadframe, and with a chip edge of one of them kept in intimate contact with a chip edge of the other. Thus, heat conducts via those chip edges with increased efficiency, permitting the heat generated in the power supply element to quickly conduct to the control IC. This prevents heat-induced breakdown to which a MOS semiconductor is susceptible. The power supply element fabricated by a MOS process can be a horizontal structure so that a current flows from one part of the top surface of the chip to another. This makes it easy to reduce power loss. The power supply element and the control IC can be die-bonded with a single type of die-bonding paste.

The invention provides a rail-to-rail output circuit of a high-speed fully-differential amplifier and the high-speed fully-differential amplifier. The structural design of a high-speed transconductance amplification stage and a novel complementary common-emitter push-pull output stage is combined; therefore, high-speed transconductance amplification and buffering can be carried out on a differential signal output by a pre-stage of the amplifier, and rail-to-rail output close to a positive / negative power supply is realized; through a feedback network arranged between the output end and the input end, the frequency roll-off can be effectively compensated, and the output stability is improved; the rail-to-rail output circuit is realized based on a complementary bipolar process and an all-longitudinal transistor, and high-speed amplification and rail-to-rail output are realized while a high-speed operational amplifier is ensured to be applied by reducing power supply voltage, so the signal-to-noise ratio and the speed / bandwidth index of the rail-to-rail output circuit are not influenced.

The invention discloses a low-noise operational amplifier circuit. The low-noise operational amplifier circuit comprises an amplifier circuit, and an amplifier comprises an input-stage circuit, an intermediate-stage circuit and an output-stage circuit. The input stage circuit adopts a differential pair transistor structure to improve input impedance, reduce offset voltage and temperature drift, establish a good matching direct current working point and finish buffering and first stage amplification of input voltage; the intermediate-stage circuit adopts a folding common-base-stage common-emitter-stage structure to improve voltage gain and output swing; the output-stage circuit adopts triodes with the same parameters to output in a push-pull manner to expand internal current, so that the post-stage driving capability is improved, and the output swing is increased. According to the invention, the input voltage noise is optimized by changing the size of the resistor, and the polycrystalline silicon trimming replaces the laser trimming of the metal film resistor, so that the characteristic of high precision of the circuit is realized. According to the circuit structure, the noise performance can be improved, and the circuit structure can be compatible with an existing anti-radiation standard bipolar process.

The invention discloses a composite magnetic field sensor and a manufacturing process thereof. The composite magnetic field sensor comprises a magnetic sensitive transistor and a tunneling magnetic resistor (TMR) composited on the magnetic sensitive transistor. The collector region of the magnetic sensitive transistor is arranged above the emitter region. The base region is arranged at one side of the emitter region and the collector region, and is manufactured in a silicon corrosion pit. The carrier injection ability of the base region is improved, and the magnetic sensitivity of the magnetic sensitive transistor is improved. The composite magnetic field sensor is prepared by combining the manufacturing process with a microelectronic mechanical system (MEMS) technology, a bipolar process and a nano film preparation technology. The composite magnetic field sensor combining the magnetic sensitive transistor and the tunneling magnetic resistor has both the strong magnetic field detection performance of the magnetic sensitive transistor and the weak magnetic field detection performance of the tunneling magnetic resistor. Thus, wide-range magnetic field detection is realized.

In order to highlight the characteristics of the coordination effect of the displacement damage and the total ionization dose of the bipolar process electronic device, the invention provides a test method for the coordination effect of the displacement damage and the total ionization dose of the bipolar process electronic device, which comprises the following steps of: firstly, irradiating the bipolar process electronic device by using gamma rays; in the irradiation process, a corresponding device adopting one of a variable-temperature irradiation mode and a constant-high-temperature irradiation mode, and performing irradiation until the required ionization total dose level is reached; and then irradiating the irradiated electronic device to a specified value by using reactor neutrons, whererin in the irradiation process, no bias is applied to the device and pins are in short-circuiting; and after neutron irradiation, testing the electrical parameters of the device after the amount of the surface active agent of the device is reduced to a safety threshold. According to the method, the combined action of oxide trapped charges, interface traps and displacement damage defects can be emphasized, so that conservative evaluation of the displacement damage and ionization total dose coordination effect of the bipolar process electronic device in a complex radiation environment is realized.

The invention discloses a programmable delay setting circuit and a working method. The method changes the magnitude of discharge current of a constant current source to a delay capacitor in a circuitby changing the size of an external delay resistor, thereby changing the discharge time and controlling a phase difference of four path output time of a phase shift resonant PWM controller. Moreover,zero delay setting can also be achieved by setting a DELAYSET end open circuit or an external high level voltage to turn off the constant current source. Circuit test results show that under differentexternal delay resistor conditions, the delay can be flexibly achieved at any time, including zero delay. The method can be fully compatible with a standard bipolar process, can be widely applied toa high-efficiency switching power supply chip design, and have good application prospects and economic benefits.

The invention provides a current-limiting protection circuit of a bipolar process switching power supply. The constant current generated by a current mirror flows through a resistor to obtain resistance voltage drop, and the resistance voltage drop is compared with conduction voltage drop of a power MOS (Metal Oxide Semiconductor) tube to judge whether the current of the power tube exceeds a set maximum value or not, so that the grid voltage of the power MOS tube is adjusted to play a current-limiting role. The invention provides a current-limiting protection design mode which is simple in structure and low in power consumption for a switching power supply system using a bipolar process circuit to drive a power MOS (Metal Oxide Semiconductor) tube. By setting the proportional relation between the resistor and the voltage drop of the MOS tube, the current-limiting protection threshold value can be accurately and flexibly set, and adjustment and design are facilitated. The defect that efficiency is affected by resistance loss due to the fact that a traditional circuit adopts a trigger mode of outputting series resistance sampling resistance drop is overcome.

A manufacture method of an all-dielectric isolation silicon on insulator (SOI) material sheet for a complementary bipolar process comprises of the steps of manufacturing an N-type buried layer and a P-type buried layer on a first monocrystalline wafer, performing deep-trench etching, sacrificial layer oxidation, trench resistor oxidation and deposition trench filling of polycrystalline silicon and corrugated metal pipe (CMP) polycrystalline silicon on the first monocrystalline wafer to form a dielectric isolation region; arranging a buried oxide layer on a second monocrystalline wafer; performing front silicon bonding of the first monocrystalline wafer with the formed dielectric isolation region and the second monocrystalline wafer with the formed buried oxide layer; and performing reduction and CMP finishing polish of a substrate on the side of the first monocrystalline wafer, and finally forming the all-dielectric isolation SOI material sheet for the complementary bipolar process. The manufacture method has the advantages of being low manufacture cost, few in active layer defects, good in active layer parameter consistency, free of figure drifting and the like, and can be widely applied to the manufacture field of the all-dielectric isolation complementary bipolar process.

The invention discloses a silicon-based APD integrated circuit, which belongs to the technical field of optoelectronic integration. The silicon-based APD integrated circuit comprises a substrate, a silicon-based avalanche photodiode (APD), a photovoltaic diode array, a bipolar NPN transistor and a management circuit formed by resistors and capacitors, wherein a plurality of groups of V-type grooves are arranged in the substrate; the silicon-based avalanche photodiode, the photovoltaic diode array and the bipolar NPN transistor are arranged in one V-type groove and are integrated on the same substrate with the management circuit. The integrated circuit combines the traditional V-type groove process and the bipolar process, the structure is simple, the reliability is high, the crosstalk is little, and the power consumption is low.

The invention provides a dual polycrystal self-aligned complementary bipolar device structure and a fabrication method thereof. Process development of a 0.35micron technology node is achieved under the condition of a 6inch process line, namely on the process line of photoetching the technology node with the minimum linewidth of 0.5micron; fabrication of a complementary bipolar process device which can only be achieved under a higher technology level is achieved under the premise of not increasing equipment budget of the higher technology level of the 6inch process line; the actual minimum process dimension reaches 0.3-0.35micron; the device performance is not reduced, namely various technical indexes of a device all reach the technology level under the 0.35micron technology node and the characteristic frequency of the device employing an NPN tube and a PNP tube reaches the magnitude of gigahertz; and on the basis of high structure symmetry of the longitudinal NPN tube and PNP tube and high symmetry of device characteristics, a technology platform and an important guarantee are provided for improving the design capability of a push-pull circuit. Due to the adoption of the 6inch process line, the actual process fabrication cost is effectively reduced.

The invention discloses a silicon-based APD integrated circuit, which belongs to the technical field of optoelectronic integration. The silicon-based APD integrated circuit comprises a substrate, a silicon-based avalanche photodiode (APD), a photovoltaic diode array, a bipolar NPN transistor and a management circuit formed by resistors and capacitors, wherein a plurality of groups of V-type grooves are arranged in the substrate; the silicon-based avalanche photodiode, the photovoltaic diode array and the bipolar NPN transistor are arranged in one V-type groove and are integrated on the same substrate with the management circuit. The integrated circuit combines the traditional V-type groove process and the bipolar process, the structure is simple, the reliability is high, the crosstalk is little, and the power consumption is low.

The invention discloses an improved method of a semiconductor integrated general operational amplifier without a resistor and an amplifier thereof. A two-terminal device CRD (Current Regulator Diode), which is compatible with a bipolar process, directly replaces all kinds of constant current source circuits which are always used currently in a circuit. The semiconductor integrated general operational amplifier without the resistor is composed of a pre-stage circuit, an intermediate-stage circuit and a final-stage circuit. No resistance elements exist in a new circuit, and the whole circuit is simple in structure, standard in form, the pre-stage circuit and the intermediate-stage circuit are symmetric, the number of used components is greatly reduced, the size of a CRD device is much smaller than that of an integrated resistor, the integration density is improved and the power consumption is reduced; no negative feedbacks exist in the whole circuit, and the transient response of the circuits is improved greatly; and for final output, over-current protection is not required, so that even if an output end is short-circuited, the whole circuit is not damaged, thereby improving the security.

The invention discloses an over-temperature protection circuit of a bipolar linear voltage regulator and belongs to the field of over-temperature protection. The over-temperature protection circuit of the bipolar linear voltage regulator is composed of a temperature sensor circuit, a sampling feedback circuit and an output circuit. According to the over-temperature protection circuit of the bipolar linear voltage regulator, the current feedback loop is introduced, so the circuit has a temperature hysteresis characteristic, problems that the protected circuit is frequently started at a temperature protection point, the junction temperature of a chip cannot be fully reduced and the circuit cannot return to a normal working state are solved, and the over-temperature protection circuit is suitable for low power supply voltage; by adopting the over-temperature protection circuit disclosed by the invention, whether the junction temperature of the bipolar linear voltage regulator and other analog circuit chips exceeds a safe working area or not can be accurately identified. The circuit is designed and realized by adopting a bipolar process, the circuit structure is simple, the number of used components is small, and the physical design area is small.

The bipolar longitudinal NPN tube manufacturing process using phosphorus burying and deep phosphorus burying technologies is a process method for using the phosphorus burying and deep phosphorus burying technologies in the manufacturing process for the phosphorus burying and deep phosphorus burying technologies, for the purpose of reducing saturated pressure drop of NON tube and enhancing the circuit output power. The bipolar longitudinal NPN tube manufacturing process using phosphorus burying and deep phosphorus burying technologies means using phosphorus burying and deep phosphorus burying technologies in the bipolar process for manufacturing the NPN tube. The area when using phosphorus burying and deep phosphorus burying technologies is the same as the area when using common antimony burying technical chip, the extra chip area is not required and only the processes are different from each other. Material sheet using the phosphorus burying and deep phosphorus burying technologies to manufacture the NPN tube is P-type <111> crystallographic direction, resistance rate is 10 to 20 Omega.cm, and after using the deep phosphorus burying technology, the concentration and volume when the deep phosphorus is diffused too deep can be efficiently compensated owing to the upward turning effect of the deep phosphorus burying, thus settling the bottleneck problem about larger resistance at the contact position of the deep phosphorus and burying layer.

The invention discloses a bipolar process-based integrated circuit with an ultralow offset voltage. With the method of the invention adopted, the offset problem of a bipolar process-based double-input-to-single-output conversion integrated circuit system can be solved. According to the integrated circuit of the invention, a double-input-to-single-output conversion matching technology is adopted; and a base current compensation technology and a current load compensation technology are combined; and therefore, the influence of the base current of a bipolar device on system offset is reduced. Theoutput end of a double-input-to-single-output conversion matching circuit is connected with a base current compensation circuit; the base current compensation circuit is connected with the double-input-to-single-output conversion matching circuit; and a current load compensation circuit is connected with the double-input-to-single-output conversion matching circuit and the base current compensation circuit. With the integrated circuit of the invention adopted, the influence of the base current of a bipolar transistor on the offset of the circuit system is reduced, and the matching precision of the circuit is improved; the gain of the circuit is improved; and current matching is not affected by large current output. The integrated circuit is widely applied to bipolar process-based preciseoperational amplifiers, low-offset comparators and high-precision AD / DA devices and other related fields.

The invention provides a production method of a deep groove and PN junction mixed isolation structure for a bipolar technology. The method comprises the steps that a mask is arranged on a substrate silicon chip; an etching window running through the mask is arranged on the mask, the substrate silicon chip on the lower layer of the etching window is etched through the etching window, and a deep groove is formed; impurities whose doping type is opposite to that of bulk silicon are injected into the deep groove to form a groove bottom isolation PN junction; the mask is peeled off, and ONO composite film is prepared on the surface of the bulk silicon and in the deep groove; polycrystalline silicon is deposited to fill the deep groove; silicon oxide on the top layer of the ONO film outside thedeep groove is removed, and the remaining silicon nitride-silicon oxide structure is utilized to form an active area. According to the production method of the deep groove and PN junction mixed isolation structure for the bipolar technology, the stress in the groove is smartly balanced by means of the ONO structure on the inner wall of the deep groove, meanwhile the silicon nitride-silicon oxide structure is served as a masking layer of active area oxidation, extra production process of the masking layer during production of the active area is avoided, the production cost of the process is effectively reduced, and the isolation effect is improved.