43 results about "Bipolar process" patented technology

An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source / drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

Communication to or from a nanodevice is provided with a nanostructure-based antenna, preferably formed from, but not limited to, a single wall nanotube (SWNT). Other nanostructure-based antennas include double walled nanotubes, semiconducting nanowires, metal nanowires and the like. The use of a nanostructure-based antenna eliminates the need to provide a physical communicative connection to the nanodevice, while at the same time allowing communication between the nanodevice and other nanodevices or outside systems, i.e., systems larger than nanoscale such as those formed from semiconductor fabrication processes such as CMOS, GaAs, bipolar processes and the like.

An EEPROM memory cell uses silicon-germanium / silicon and emitter polysilicon film for fabricating shallow source / drain regions to increase a breakdown voltage with respect to a well. The source / drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

An EEPROM memory cell uses an emitter polysilicon film for fabricating shallow source / drain regions to increase a breakdown voltage of the wells. The wells are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

An EEPROM memory cell uses silicon-germanium / silicon and emitter polysilicon film for fabricating shallow source / drain regions to increase a breakdown voltage with respect to a well. The source / drain regions are fabricated to be approximately 100 nm (0.1 micrometers (μm)) in depth with a breakdown voltage of approximately 14 volts or more. A typical breakdown voltage of a well in a bipolar process is approximately 10 volts. Due to the increased breakdown voltage achieved, EEPROM memory cells can be produced along with bipolar devices on a single integrated circuit chip and fabricated on a common semiconductor fabrication line.

A power supply device 1 includes a control IC 3 fabricated by a bipolar process and a power supply element 4 fabricated by a MOS process, and has them die-bonded on a leadframe 2, with a chip edge of one of them kept in intimate contact with a chip edge of the other. Thus, heat conducts via those chip edges with increased efficiency, permitting the heat generated in the power supply element 4 to quickly conduct to the control IC 3. This prevents heat-induced breakdown to which a MOS semiconductor is susceptible. The power supply element 4 fabricated by a MOS process does not need to have a vertical structure as a bipolar PNP transistor does, and can a horizontal structure so that a current flows from one part of the top surface of the chip to another. This makes it easy to reduce power loss. Thus, the power supply element 4 and the control IC 3 can be connected, at the bottom surfaces of their chips, to a common GND potential, and can thus be together die-bonded with a single type of die-bonding paste as exemplified by Ag paste 5. This prevents electrostatic breakdown to which a bipolar semiconductor is susceptible.

A power supply device includes a control IC fabricated by a bipolar process and a power supply element fabricated by a MOS process, both of them die-bonded on a leadframe, and with a chip edge of one of them kept in intimate contact with a chip edge of the other. Thus, heat conducts via those chip edges with increased efficiency, permitting the heat generated in the power supply element to quickly conduct to the control IC. This prevents heat-induced breakdown to which a MOS semiconductor is susceptible. The power supply element fabricated by a MOS process can be a horizontal structure so that a current flows from one part of the top surface of the chip to another. This makes it easy to reduce power loss. The power supply element and the control IC can be die-bonded with a single type of die-bonding paste.

In order to highlight the characteristics of the coordination effect of the displacement damage and the total ionization dose of the bipolar process electronic device, the invention provides a test method for the coordination effect of the displacement damage and the total ionization dose of the bipolar process electronic device, which comprises the following steps of: firstly, irradiating the bipolar process electronic device by using gamma rays; in the irradiation process, a corresponding device adopting one of a variable-temperature irradiation mode and a constant-high-temperature irradiation mode, and performing irradiation until the required ionization total dose level is reached; and then irradiating the irradiated electronic device to a specified value by using reactor neutrons, whererin in the irradiation process, no bias is applied to the device and pins are in short-circuiting; and after neutron irradiation, testing the electrical parameters of the device after the amount of the surface active agent of the device is reduced to a safety threshold. According to the method, the combined action of oxide trapped charges, interface traps and displacement damage defects can be emphasized, so that conservative evaluation of the displacement damage and ionization total dose coordination effect of the bipolar process electronic device in a complex radiation environment is realized.

A manufacture method of an all-dielectric isolation silicon on insulator (SOI) material sheet for a complementary bipolar process comprises of the steps of manufacturing an N-type buried layer and a P-type buried layer on a first monocrystalline wafer, performing deep-trench etching, sacrificial layer oxidation, trench resistor oxidation and deposition trench filling of polycrystalline silicon and corrugated metal pipe (CMP) polycrystalline silicon on the first monocrystalline wafer to form a dielectric isolation region; arranging a buried oxide layer on a second monocrystalline wafer; performing front silicon bonding of the first monocrystalline wafer with the formed dielectric isolation region and the second monocrystalline wafer with the formed buried oxide layer; and performing reduction and CMP finishing polish of a substrate on the side of the first monocrystalline wafer, and finally forming the all-dielectric isolation SOI material sheet for the complementary bipolar process. The manufacture method has the advantages of being low manufacture cost, few in active layer defects, good in active layer parameter consistency, free of figure drifting and the like, and can be widely applied to the manufacture field of the all-dielectric isolation complementary bipolar process.

Communication to or from a nanodevice is provided with a nanostructure-based antenna, preferably formed from, but not limited to, a single wall nanotube (SWNT). Other nanostructure-based antennas include double walled nanotubes, semiconducting nanowires, metal nanowires and the like. The use of a nanostructure-based antenna eliminates the need to provide a physical communicative connection to the nanodevice, while at the same time allowing communication between the nanodevice and other nanodevices or outside systems, i.e., systems larger than nanoscale such as those formed from semiconductor fabrication processes such as CMOS, GaAs, bipolar processes and the like.

The invention discloses a silicon-based APD integrated circuit, which belongs to the technical field of optoelectronic integration. The silicon-based APD integrated circuit comprises a substrate, a silicon-based avalanche photodiode (APD), a photovoltaic diode array, a bipolar NPN transistor and a management circuit formed by resistors and capacitors, wherein a plurality of groups of V-type grooves are arranged in the substrate; the silicon-based avalanche photodiode, the photovoltaic diode array and the bipolar NPN transistor are arranged in one V-type groove and are integrated on the same substrate with the management circuit. The integrated circuit combines the traditional V-type groove process and the bipolar process, the structure is simple, the reliability is high, the crosstalk is little, and the power consumption is low.

The invention provides a band gap reference starting circuit and method based on a radiation resistance double-pole technology and used for a wide power source range. It is ensured that when power supply is low, normal work of the band gap reference circuit is not influenced, and the circuit is applied to the wide power source range. The circuit comprises the band gap reference circuit and a starting circuit body which are connected; the starting circuit body is composed of a Zener diode D1, a resistor R1, a first double-pole transistor set and a second double-pole transistor set. By means ofthe starting method, the difference of breakdown voltage BV of the Zener diode D1 and junction voltage of triodes Q1, Q4 and Q16 can generate current irrelevant to power source voltage and with a certain temperature coefficient on resistors R2 and R3. As to the circuit, through R6, a triode Q6 and a triode Q7, compensation current with the temperature coefficient opposite to that of the current isgenerated, and after the two pieces of current flow through a triode Q13, reference current with temperature compensation properties is finally formed, then flows out of a collector of a pipe 15 through the mirror image effect of a triode Q14 and is provided for other circuit modules.

The invention relates to a method for suppressing an oxide in a bipolar process electronic component from capturing positive charge formation. By the method, the problem that charges are captured by the oxide in an existing bipolar process electronic component due to radiation to change carrier surface recombination rate and further affect minority carrier lifetime is solved. The method comprisesthe steps of 1, determining a chip thickness a of a sample; 2, calculating an incident depth d of incident particles in the sample chip; 3, calculating ionization absorption dosage Id and displacementabsorption dosage Dd; 4, allowing log[(Id+Dd) / Dd]; 5, adjusting irradiation flux or dosage rate of the incident particles; 6, performing primary irradiation sample; and 7, performing secondary irradiation and completing. By the method of changing the irradiation flux or the dosage rate, the problem of capturing the positive charges by the oxide in an electronic device is prevented, and the methodis used for suppressing the oxide in the electronic component from capturing the positive charges.

The bipolar longitudinal NPN tube manufacturing process using phosphorus burying and deep phosphorus burying technologies is a process method for using the phosphorus burying and deep phosphorus burying technologies in the manufacturing process for the phosphorus burying and deep phosphorus burying technologies, for the purpose of reducing saturated pressure drop of NON tube and enhancing the circuit output power. The bipolar longitudinal NPN tube manufacturing process using phosphorus burying and deep phosphorus burying technologies means using phosphorus burying and deep phosphorus burying technologies in the bipolar process for manufacturing the NPN tube. The area when using phosphorus burying and deep phosphorus burying technologies is the same as the area when using common antimony burying technical chip, the extra chip area is not required and only the processes are different from each other. Material sheet using the phosphorus burying and deep phosphorus burying technologies to manufacture the NPN tube is P-type <111> crystallographic direction, resistance rate is 10 to 20 Omega.cm, and after using the deep phosphorus burying technology, the concentration and volume when the deep phosphorus is diffused too deep can be efficiently compensated owing to the upward turning effect of the deep phosphorus burying, thus settling the bottleneck problem about larger resistance at the contact position of the deep phosphorus and burying layer.

The invention provides a production method of a deep groove and PN junction mixed isolation structure for a bipolar technology. The method comprises the steps that a mask is arranged on a substrate silicon chip; an etching window running through the mask is arranged on the mask, the substrate silicon chip on the lower layer of the etching window is etched through the etching window, and a deep groove is formed; impurities whose doping type is opposite to that of bulk silicon are injected into the deep groove to form a groove bottom isolation PN junction; the mask is peeled off, and ONO composite film is prepared on the surface of the bulk silicon and in the deep groove; polycrystalline silicon is deposited to fill the deep groove; silicon oxide on the top layer of the ONO film outside thedeep groove is removed, and the remaining silicon nitride-silicon oxide structure is utilized to form an active area. According to the production method of the deep groove and PN junction mixed isolation structure for the bipolar technology, the stress in the groove is smartly balanced by means of the ONO structure on the inner wall of the deep groove, meanwhile the silicon nitride-silicon oxide structure is served as a masking layer of active area oxidation, extra production process of the masking layer during production of the active area is avoided, the production cost of the process is effectively reduced, and the isolation effect is improved.