67results about How to "Save board space" patented technology

A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.

An improved electrical circuit that includes an embedded electrical component and an embedded voltage variable material (“VVM”) is provided. In one embodiment, the embedded VVM is provided as a voltage variable substrate, which is used in combination with an embedded electrical component, such as an embedded resistive material or an embedded capacitive material.

There is disclosed an improved differential amplifier (20) having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit (11) connected to said preceding stage, a buffer (22) and an amplification section (12) connected in series in the direct amplification line, a first amplifier (16), a RC network (17′) and a second amplifier (23) connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block (21) is to respectively isolate the input signal and the feedback signal from the summing nodes (A′,B′) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset. In addition, the input impedance matching represented by parameter S11 is considerably improved.

Systems and methods may be implemented in a power device subsystem topology to provide an arbitration and communication scheme between a single consolidated non-volatile random access (NVRAM) memory device and multiple discrete digital power controller devices in a manner that provides data protection and the ability to update the full NVRAM content when needed.

The invention provides a GOA circuit and a display device. The GOA circuit comprises cascaded GOA units, wherein each GOA unit comprises a pull-up control unit, a pull-up unit, a pull-down unit and a pull-down maintenance unit; and each pull-down maintenance unit comprises a pull-down maintenance module, a first pull-down module and a second pull-down module. Every two adjacent GOA units are gathered into one group, wherein by virtue of the pull-down maintenance module of the superior GOA unit, the first pull-down module in the superior GOA unit and the second pull-down module in the subordinate GOA unit are controlled so as to keep potentials of grid signal points and horizontal scanning signals of the superior GOA unit and the subordinate GOA unit at low potentials, and by virtue of the pull-down maintenance module of the subordinate GOA unit, the first pull-down module in the subordinate GOA unit and the second pull-down module in the superior GOA unit are controlled so as to keep potentials of grid signal points and horizontal scanning signals of the subordinate GOA unit and the superior GOA unit at low potentials. The invention can diminish an occupied space of the GOA circuit and can bring about benefits for the implementation of a narrow-bezel display panel.

A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and an outline suitable for attaching a semiconductor chip. A first FET chip (220) is vertically stacked to the opposite pad surface. A clip (240) is vertically stacked on the first FET chip and tied to a lead (202, grounded output terminal). A second FET chip (210) has its source terminal attached to the recessed portion and its drain (210a, input terminal) and gate (210b) terminals co-planar with the un-recessed portion. A driver-and-controller chip (230) is attached to the clip. Packaging compound (290) encapsulates the parts but leaves a pad surface and the drain and gate terminals of the second FET chip un-encapsulated.

A connector assembly (1) used to interconnect a primary circuit board (4) to an intermediate circuit board (5) includes a one-piece insulated housing (2) and an outer shell (3) partially enclosing outside of the housing (2). The housing (2) has a space (20) formed from a mounting side of the housing (2) to the primary circuit board (4) and a face (22) formed at another mounting side of the housing (2) to the intermediate circuit board (5). A plurality of conductors (25) is retained in the housing and extends from the space (20) to the face (22) and each conductor (25) has one tail portion (251) to be press-fit on the intermediate circuit board (5) and another tail portion to be engaged with a corresponding hole (41) on the primary circuit board (4). The one-piece housing and fewer interfaces are used, and the mounting method and mechanism of the conductors is simplified to reduce the cost of manufacturing.

An ergonomic, self contained hand-held thread inspection tool is power driven, which uses a mechanical clutch as a surrogate for torque to initiate automatic reversal and gauge withdrawal in case of jamming. The distal end carries the thread gauge attached to a motor-driven spindle. A thread depth collar sleeve, adjustable by manual turning, concentrically surrounds the thread gauge. When threaded into a blind hole or onto a protruding stud and operated, the distal end of the thread depth collar sleeve comes in contact with a part, pushing it against spring force. This movement is internally sensed, causing an indicator to flash, signaling “test OK”, while automatically reversing the spindle to withdraw the thread gauge. If during the forward excursion of the thread gauge a torque exceeding the pre-set torque limit is encountered, a buzzer is sounded signaling an over-torque problem and the spindle is simultaneously reversed for automatic gauge withdrawal.

An improved electrical circuit that includes an embedded electrical component and an embedded voltage variable material (''VVM'') is provided. In one embodiment, the embedded VVM is provided as a voltage variable substrate, which is used in combination with an embedded electrical component, such as an embedded resistive material or an embedded capacitive material.

The present invention comprises a lead frame substrate adapted to receive semiconductor die and multiple passive components. The lead frame substrate is preferably formed from a single piece of electrically conductive material, such as copper, and may be mounted within a lead frame package or directly onto a circuit board. The lead frame substrate includes mounting surfaces adapted to receive the semiconductor dice and passive components. The mounting surfaces are linked together by temporary and / or permanent connection bars. A method to manufacture the lead frame package includes, among other steps, forming a lead frame substrate, applying a molding compound to the lead frame substrate to fix each mounting surface and connection bar in place, removing the temporary connection bars, mounting the semiconductor components on the lead frame substrate, and applying a packaging material over the lead frame substrate to encapsulate the semiconductor components.

An electrical connector is provided in the present invention, including an insulating housing, multiple power terminals and multiple signal terminals. The insulating housing has at least one upright power receptacle body and at least one upright signal plug body parallel to the power receptacle body. Wherein the power receptacle body forms an upright power port on a front surface thereof, and the signal plug body forms at least one signal port on a front surface thereof. Each power terminal has a plate-shaped base plate, at least one spring connection end and multiple tails. The power receptacle body and the signal plug body of the present invention are designed to be upright for saving the edge space of a circuit board. Moreover, the electrical connector of the present invention also has a character of zero insertion force by controlling the length of the signal terminal and the power terminal.

The invention discloses a wireless power supply system used for printed circuit boards, relates to the field of wireless electric energy transmission, and solves the problems of complicated routing and poor power supply quality which are caused by existing power supply modes adopting externally connected power lines, and poor anti-jamming capability of the printed circuit boards. A transmitter circuit of the wireless power supply system used for printed circuit boards is used for inverting direct current into alternating current with an f frequency and sending out an alternating magnetic field with the f frequency; each receiving circuit is used for sensing the alternating magnetic field generated by the transmitter circuit and generating alternating current with the f frequency; and the alternating current is performed with rectification and voltage stabilization and then supplies power for a branch circuit. The wireless power supply system used for printed circuit boards is suitable for wireless power supply of printed circuit boards.

Disclosed is an SRIO interconnection exchanging device based on an FPGA. An SRIO interconnection module, FIFO modules and an SRIO interface module are arranged in the FPGA. Data of all source apparatuses enter the SRIO interconnection module through the SRIO interface module and then enter the FIFO module after being scheduled by the SRIO interconnection module, and the FIFO module transmits the data to the SRIO interface module which outputs the data to target apparatuses. Given that the SRIO interface module supplies n interfaces, each interface supports one apparatus, the SRIO interconnection module supplies an arbiter for each apparatus, and an FIFO module is set corresponding to each apparatus. When the apparatus connected with certain interface is a target apparatus, the corresponding arbiter of the target apparatus performs time division slicing scheduling on data input from the interfaces of all source apparatuses according to data packets, and the scheduled data packets are output from corresponding SRIO interfaces through the corresponding FIFO modules.

The present invention relates in a first aspect to a galvanically isolated power converter assembly comprising a first set of electrically interconnected resonant power inverters configured for generating respective output voltages and output currents. The galvanically isolated power converter assembly further a first positive summing node and a first negative summing node configured to combining the output voltages and output currents of the first set of resonant power inverters and a first common load circuit comprising a positive load input and a negative load input. A galvanic isolation barrier comprises first and second common isolation capacitors electrically insulating the common load circuit. Each of the first and second common isolation capacitors possesses an official safety rating.

A digital storage device includes primarily a multi-memory card interface and a USB interface integrated into a common bus which is complied with the specification of a USB junction. A connection circuit between the common bus and a flash memory is formed by a related switch circuit, so as to constitute a digital storage device which is provided with a transmission function for a plurality of memories, and can perform a signal access with a USB transmission interface or a multi-memory card transmission interface including an SD transmission interface, an MMC transmission interface, an MS PRO transmission interface, an XD transmission interface, an SM transmission interface, and a CF transmission interface of an electronic device, by interconnecting with a corresponding connection port through the single common bus.

An ergonomic, self contained hand-held thread inspection tool is power driven, which uses a mechanical clutch as a surrogate for torque to initiate automatic reversal and gauge withdrawal in case of jamming. The distal end carries the thread gauge attached to a motor-driven spindle. A thread depth collar sleeve, adjustable by manual turning, concentrically surrounds the thread gauge. When threaded into a blind hole or onto a protruding stud and operated, the distal end of the thread depth collar sleeve comes in contact with a part, pushing it against spring force. This movement is internally sensed, causing an indicator to flash, signaling “test OK”, while automatically reversing the spindle to withdraw the thread gauge. If during the forward excursion of the thread gauge a torque exceeding the pre-set torque limit is encountered, a buzzer is sounded signaling an over-torque problem and the spindle is simultaneously reversed for automatic gauge withdrawal.

A changeable USB memory stick includes primarily a common bus which is provided with a multi-memory card interface and a USB interface. The common bus is complied with the format of a USB junction, and is provided with a transmission function of a plurality of memories. The USB memory stick can perform a signal access with a USB transmission interface or a multi-memory card transmission interface including an SD transmission interface, an MMC transmission interface, an MS PRO transmission interface, an XD transmission interface, an SM transmission interface, and a CF transmission interface of an electronic device, by interconnecting with a corresponding connection port through the single common bus.

An electrical connector is provided in the present invention, including an insulating housing, multiple power terminals and multiple signal terminals. The insulating housing has at least one upright power receptacle body and at least one upright signal plug body parallel to the power receptacle body. Wherein the power receptacle body forms an upright power port on a front surface thereof, and the signal plug body forms at least one signal port on a front surface thereof. Each power terminal has a plate-shaped base plate, at least one spring connection end and multiple tails. The power receptacle body and the signal plug body of the present invention are designed to be upright for saving the edge space of a circuit board. Moreover, the electrical connector of the present invention also has a character of zero insertion force by controlling the length of the signal terminal and the power terminal.

A digital seismic sensor adapted to be connected, via a two-conductor line, to an acquisition device. The digital seismic sensor includes: a digital sensor; a local sampling clock providing a sampling frequency; a receiver for receiving command data coming from the acquisition device and synchronization information providing accurate timing information to enable seismic sensor synchronization; a compensator for compensating, as a function of the synchronization information, a drift of the local sampling clock; a transmitter for transmitting seismic data towards the acquisition device; a driver for driving the receiver and the transmitter, according to a half-duplex transmission protocol over the two-conductor line and using a transmission clock extracted from the received command data; a power receiver for receiving electrical power; and a coupler for coupling the command and synchronization information receiver, the transmitter and the power receiver to the two-conductor line.

The embodiment of the invention provides an antenna tuning method and a terminal. The method comprises the steps of obtaining a first working frequency band of a first antenna under the condition that the first antenna is in a working state and a second antenna is in a standby state; determining a target radio frequency path corresponding to the first working frequency band in the at least two second radio frequency paths according to a preset corresponding relation between the working frequency band of the first antenna and the at least two second radio frequency paths; and controlling the second power amplification unit to conduct the second antenna and the target second radio frequency. According to the embodiment of the invention, the radiation power of the antenna in the working state is adjusted by utilizing other antennas and the load on the radio frequency path which can be connected with the other antennas, so that the antenna can work with better working efficiency, thereby saving the use of an antenna tuner and reducing the production cost of the terminal.

A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and an outline suitable for attaching a semiconductor chip. A first FET chip (220) is vertically stacked to the opposite pad surface. A clip (240) is vertically stacked on the first FET chip and tied to a lead (202, grounded output terminal). A second FET chip (210) has its source terminal attached to the recessed portion and its drain (210a, input terminal) and gate (210b) terminals co-planar with the un-recessed portion. A driver-and-controller chip (230) is attached to the clip. Packaging compound (290) encapsulates the parts but leaves a pad surface and the drain and gate terminals of the second FET chip un-encapsulated.

Techniques are provided for synchronously transmitting data in parallel from an external memory device to a destination circuit using a sequential read mode. The memory device includes an address counter. The address counter generates sequential read addresses for the data bits stored in the memory device. The destination circuit generates a clock signal that controls the address counter. The destination circuit can also transmit a start address to the memory device. The address counter sequentially generates a new read address in response to transitions in the clock signal beginning with the start address. Data bits are transferred in parallel from the memory device to the destination circuit.

The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing uniform straight through routing. Also, the straight through routing and pin locations are matched to allow those straight routing lines to mate directly to high speed lines. Also, straight ground lines having a single via are associated with the straight through routing lines.

The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing uniform straight through routing. Also, the straight through routing and pin locations are matched to allow those straight routing lines to mate directly to high speed lines. Also, straight ground lines having a single via are associated with the straight through routing lines.

A digital seismic sensor adapted to be connected, via a two-conductor line, to an acquisition device. The digital seismic sensor includes: a digital sensor; a local sampling clock providing a sampling frequency; a receiver for receiving command data coming from the acquisition device and synchronization information providing accurate timing information to enable seismic sensor synchronization; a compensator for compensating, as a function of the synchronization information, a drift of the local sampling clock; a transmitter for transmitting seismic data towards the acquisition device; a driver for driving the receiver and the transmitter, according to a half-duplex transmission protocol over the two-conductor line and using a transmission clock extracted from the received command data; a power receiver for receiving electrical power; and a coupler for coupling the command and synchronization information receiver, the transmitter and the power receiver to the two-conductor line.

The invention discloses a method and a system for realizing multi-serial port switching based on a CPLD, and a board card. The method comprises the following steps: acquiring a control enable signal and a plurality of groups of UART signals from a UART module in a control end BMC; determining a UART signal to be output from the plurality of groups of UART signals by using a CPLD according to the control enable signal; and outputting the UART signal to be output by using an external connector. The system comprises a signal acquisition module, a to-be-output signal determination module and an external connector. The board card comprises a BMC and a system for achieving multi-serial-port switching based on a CPLD. Through the method and the system, flexible switching of the serial ports can be achieved, the accuracy and switching efficiency of serial port switching can be improved, and the board space and the material cost can be effectively saved.

A plug connector, a receptacle connector and an electrical connector assembly are disclosed. When the plug connector is engaged with the receptacle connector, the power mating bodies and the signal mating body of the receptacle connector respectively enter into the corresponding plug power ports and the plug signal port of the plug connector, and the plug power contacts and the plug signal contacts respectively enter into the receptacle power ports and the receptacle signal ports. The vertical blade-shaped mating end of the plug power contact is inserted between the elastic pieces of the corresponding two receptacle power contacts, and the head of the plug signal contact is inserted into the forked head of the corresponding receptacle signal contact.

The present invention comprises a lead frame substrate adapted to receive semiconductor die and multiple passive components. The lead frame substrate is preferably formed from a single piece of electrically conductive material, such as copper, and may be mounted within a lead frame package or directly onto a circuit board. The lead frame substrate includes mounting surfaces adapted to receive the semiconductor dice and passive components. The mounting surfaces are linked together by temporary and / or permanent connection bars. A method to manufacture the lead frame package includes, among other steps, forming a lead frame substrate, applying a molding compound to the lead frame substrate to fix each mounting surface and connection bar in place, removing the temporary connection bars, mounting the semiconductor components on the lead frame substrate, and applying a packaging material over the lead frame substrate to encapsulate the semiconductor components.

A circuit board having a VCO that can be adjusted during manufacturing is disclosed. The VCO has a resonating circuit, a coupling circuit, and an oscillating circuit. The coupling circuit and the oscillating circuit have adjustable capacitors composed of micro-strips on two conductive layers of the circuit board with an insulation layer between the two conductive layers. The micro-strips are cut in different directions by laser beams to adjust the capacity of the capacitors or to make the capacitor react as inductance so that the output frequency and the phase noise of the VCO is accurate or good enough to improve the production's yield rate.

The invention relates to a serial port level conversion method. The serial port level conversion method is characterized in that a negative voltage is provided to control a positive voltage through the cooperation of a transistor. When the transistor is on voltage is positive and when the transistor is off voltage is negative, and serial port level output conversion is achieved. The serial port level input conversion and state reversion are achieved through on-off of the transistor. The negative voltage is generated by oscillation. The realization of the scheme of the level conversion is changed from a traditional chip to discrete devices. The used discrete devices are an audion, a resistor and the like. The discrete devices are low in price, and few discrete devices are needed. The level conversion function is realized and cost is lower than the cost when the chips are used.