52results about How to "Reduce read operations" patented technology

A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CASP6, which is enabled in the write and read operations, and a signal WT6RD5Z, which is enabled in the write operation and disabled in the read operation. Accordingly, unnecessary current consumed in the read operation can be reduced.

A column circuit that amplifies signals read from a sense amplifier array SAA to local input / output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input / output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.

Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of the columns comprises: a column virtual ground node; a column switch for selectively coupling the column virtual ground node to one of a ground or a nominal low voltage; and a plurality of segments. Each of the segments comprises: a segment virtual ground node; a plurality of SRAM cells including a virtual ground signal coupled to the segment virtual ground node; and a virtual ground switch for selectively coupling the segment virtual ground node to one of either a nominal low voltage or the column virtual ground node. A method for operating the SRAM cell array is also described.

An SRAM control circuit with a power saving function is disclosed, which uses an address comparator to compare a current address and a previous address in an SRAM read operation. When the two addresses are the same, data is outputted directly from a buffer without enabling a memory unit, thereby saving power.

The present invention concerns an apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to read a data signal in response to a read enable signal. The second circuit may be configured to generate the read enable signal. The third circuit may be configured to present the data signal in response to a first state of the read enable signal and present a predetermined value in response to a second state of the read enable signal.

The invention discloses an urban pipe line detection data fast mapping method and system based on a GIS platform. The method includes the steps that pipe line starting point and ending point coordinate fields are added, and value assignment is carried out on pipe line starting point and ending point coordinates; starting point and ending point coordinate information of pipe lines is directly read during pipe line mapping by carrying out value assignment on all endpoint spatial positions needed by the pipe lines so that the repeated operation of reading the pipe point coordinate information through the relation between the pipe lines and pipe points during mapping can be avoided; pipe line list mapping is carried out, wherein a pipe line list is read and traversed, the pipe lines are drawn, and pipe line attributes are read and assigned to pipe line elements; pipe point list mapping is carried out, wherein a pipe point list is read and traversed, pipe points are drawn according to point coordinate information, and pipe point attributes are read and assigned to pipe point elements; mapping is finished. According to the method, more work is completed before pipe line mapping on the basis that the pipe line mapping principle is understood, so that frequent database reading operation is simplified in the mapping process, especially for mapping with a large data volume.

The invention relates to an SSD abnormal power-down recovery method based on block growth record and a system thereof. The SSD abnormal power-down recovery method based on the block growth record comprises the following steps of S1 acquiring the physical address vpn1 of the lpn data to be recovered and the corresponding time stamp ts1, and searching according to the original mapping table to obtain the original pmt0 corresponding to the lpn; S2 judging whether the block indicated by pmt0 is a newly added conflict block; If yes, entering S4; If not, entering S3; S3 updating pmt0 to vpn1; S4 reading the guide physical address vpn0 by pmt0, and obtaining the data timestamp ts0; S5 setting the pmt of the lpn according to the timestamp ts1 and the timestamp ts0. The invention avoids the block-level scanning of the whole disk and rapidly locates the recovered object, reduces the read operation of NAND in the recovery process, greatly improves the efficiency of data recovery, and better meetsthe needs.

A non-volatile storage device in which power consumption is reduced by providing reduced read pass voltages on unselected word lines during a read operation. A programming status of one or more unselected word lines which are after a selected word line on which storage elements are being read is checked to determine whether the unselected word lines contain programmed storage elements. When an unprogrammed word line is identified, reduced read pass voltages are provided on that word line and other word lines which are after that word line in a programming order. The programming status can be determined by a flag stored in the word line, for instance, or by reading the word line at the lowest read state. The unselected word lines which are checked can be predetermined in a set of word lines, or determined adaptively based on a position of the selected word line.

The invention discloses a multi-parallel acceleration method for CNN full-connection layer operation, and the method greatly reduces the reading operation of full-connection layer parameters, effectively saves the energy consumption, and improves the energy efficiency ratio of a system through employing the sparsity characteristics of an operation result of a convolutional neural network and interpreting the numerical value of a convolution layer processing result of the convolutional neural network in advance. By utilizing the characteristics of hardware resource reuse, strong expansion capability and the like of programmable logic devices such as an FPGA and constructing a parallel pipeline multiply-accumulate architecture, the processing time is effectively saved, and the processing efficiency is improved; by comprehensively analyzing factors such as target type data, target characteristic difference and error tolerance in an application process, a processing data format is reasonably set, so that the access efficiency of data and parameters is effectively improved while the processing precision is ensured, and the purpose of multi-parallel acceleration of a full connection layer is achieved.

The invention discloses a local caching method and device based on a lease lock mechanism. The method comprises the steps of when a storage system receives a data access request sent by a client, determining a priority of the client; sending lease authority to the client according to the priority of the client; and sending target data to the client for caching, thereby enabling the client to operate the cached target data according to the lease authority. Through the lease lock mechanism, the client can cache data in the storage system to the local client, so data exchange processes between the client and a server in which the storage system is located are reduced, read operations for files and the operations for a path list are reduced, paths are shortened, the delay is reduced, and the data access capability of the storage system is improved.

Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

A novel NVM-based 2T or 2nT NAND-cell for a NAND-array for PLD, PAL and matching functions is disclosed. The preferable NVM cell can be ROM or Flash. The 2T flash cell preferably uses FN for both program and erase operation, while 2T ROM cell preferably to use phosphorus for ROM code implant to get negative Vt0.

A magnetic memory is provided in which the margin between a write current and a read current can be reduced. A magnetic storage element includes: a first magnetic layer in which the direction of magnetization can be reversed; a second magnetic layer in which the direction of magnetization is fixed; and a non-magnetic layer which is interposed between the first and second magnetic layers. The write current and the read current are supplied to the magnetic storage element in the stacking direction thereof through a read-write line. Moreover, a bias line which can apply a bias magnetic field to the first magnetic layer during a reading operation is disposed in the vicinity of the magnetic storage element.