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230results about How to "Reduce data transfer time" patented technology

Methods and applications for avoiding slow-start restart in transmission control protocol network communications

InactiveUS20050135248A1Avoid occurrence“slow-start restart” is avoidedError preventionTransmission systemsReal-time computingSlow-start
A novel approach is provided for avoiding the “slow-start restart” in TCP communications when network conditions dictate such. The disclosed approach serves to overcome the latency related to the “slow-start restart” by assessing network conditions and avoiding the “slow-start restart” when network conditions justify the avoidance. The disclosed methods, applications and devices implement the periodic communication of a probe packet that is generated and transmitted from a TCP sender to a TCP receiver during the period that the TCP network connection remains idle. Receipt of the probe packet by the TCP receiver will trigger transmission of an acknowledgment message by the TCP receiver. Upon receipt of the acknowledgement message the TCP sender will restart measurement of the idleness period and, as such the “slow-start restart” is avoided.
Owner:CORE WIRELESS LICENSING R L

Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller

A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write command on a first PCI-X bus on one side of the bridge. The target is coupled to two PCI-X masters coupled to primary and secondary memory subsystems by respective PCI-X buses on the other side of the bridge. A first FIFO buffers the write command data between the target and the first master, and a second FIFO buffers a copy of the data between the target and the second master. The first and second masters concurrently retransmit the write command on their respective PCI-X buses to the primary and secondary memory subsystems. However, the second master only retransmits if broadcasting is enabled and the write command address is in a broadcast address range known by the bus bridge.
Owner:DOT HILL SYST

Semiconductor Device

InactiveUS20070147160A1Reduce data transfer timeExpand read operation marginDigital storageSense amplifierInput/output
A column circuit that amplifies signals read from a sense amplifier array SAA to local input / output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input / output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.
Owner:LONGITUDE LICENSING LTD

Method and system for realizing ultra-low latency encoding, decoding and transmission of high-definition video

The invention provides a method and a system for realizing ultra-low latency encoding, decoding and transmission of a high-definition video. The method comprises the steps that: an encoder receives the high-definition video, segments each frame of images constituting the high-definition video into a plurality of cut frames, and completes caching, compressed encoding and uploading in sequence by regarding each of the cut frames as a unit one by one; an Ethernet transmits compressed encoded data of the cut frames; and a decoder receives the compressed encoded data of the cut frames, completes caching and independent decoding in sequence by regarding each of the cut frames as a unit, and splices the images after independent decoding to complete the restoration of each frame of the images. Themethod and the system solve the problem that high real-time video transmission application cannot be satisfied because the existing encoding and decoding system cannot cut flexibly and is difficult to adjust and optimize, realize the effect that the total time delay from encoding, transmission to decoding is less than 50 ms, and can meet the low latency requirements of the high real-time application.
Owner:HUNAN JUNHAN INFORMATION TECH CO LTD

Multicast router based on package and circuit switching technology and working mode thereof

The invention discloses a multicast router based on package and circuit switching technology and a working mode thereof. The multicast router based on package and circuit switching technology is characterized by being applied to a network on chip which includes a plurality of multicast routers, a plurality of resource nodes and a plurality of interconnection channels; each multicast router comprises an input state machine module, a priority encoder module, a decoder module, an address filtering module, an arbiter module, a crossbar module and an output state machine module; in a multicast data transmission event, a single requester node can simultaneously support sending the same batch of data to at most eight target nodes at the same time; and the success rate of establishing a link can be improved by the priority encoder module, and the target nodes are prevented from repeatedly routing by the address filtering module. The multicast router based on package and circuit switching technology can fully utilize the parallelism characteristic of the network on chip to save time consumed for the event of sending the same batch of data to the plurality of target nodes by the single requester node, and consumption on cache resources of the multicast routers in the network on chip is reduced.
Owner:HEFEI UNIV OF TECH

Arbitrary waveform generating system based on user-defined processor

The invention discloses an arbitrary waveform generating system based on a user-defined processor. In a control portion, a waveform generating module generates various waveform segment data downloaded to a hardware portion through a waveform downloading module, a control program generating module receives an externally inputted instruction set, and the instruction set is downloaded to the hardware portion after compiling of a compiling module. In the hardware portion, a storage control logic module controls reading and writing of a waveform memory, the user-defined waveform processor receives and analyzes the instruction set, generates call instructions for corresponding waveform segments according to names of the waveform segments indicated by the instruction set, transmits the call instructions to the storage control logic module and receives the waveform segment data read by the storage control logic module, and analog signals are outputted after combined waveform segment data are conditioned according to the call sequence and the call frequency of the waveform segment indicated by the instruction set. By the aid of the arbitrary waveform generating system, data transmission time of the control portion and the hardware portion during waveform generation can be shortened.
Owner:BEIJING AEROSPACE MEASUREMENT & CONTROL TECH

Imaging element, imaging apparatus, its control method, and control program

An imaging element having a layered structure including a first chip having a pixel portion in which pixels for photoelectrically converting an optical image of an object and generating a pixel signal are arranged two-dimensionally and a second chip in which a drive means of the pixel portion is arranged, and having a first output path to output the pixel signals of at least a first pixel group in the pixel portion and a second output path to output the pixel signals of a second pixel group, comprises the a conversion means for converting the pixel signals of the first and second output paths into digital signals and a control information generation means for generating control information of a photographing operation of the object by using the digital signal converted by the conversion means, wherein at least a part of the conversion means is arranged in the first chip.
Owner:CANON KK

Uplink scheduling method and apparatus in communication system

Provided is an uplink scheduling method and apparatus of a Base Station, in which total packet transmission time can be reduced by reducing the time required for a Subscriber Station to request a frequency band for packet transmission to the BS through a series of contention procedures and to be allocated to the frequency band. Therefore, even an SS that is not allocated a frequency band in an UpLink-MAP can immediately transmit a frequency band allocation request without overhead, thereby reducing initial delay time.
Owner:SAMSUNG ELECTRONICS CO LTD
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