A 3D NAND memory device is provided and includes: a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines disposed above the BSG and having a stepped configuration, and a plurality of insulation layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend along the length of the substrate to separate the BSG into a plurality of sub-BSGs. Further, one or more common source regions are formed over the substrate and extend in the lengthdirection of the substrate. One or more common source regions also extend through the BSG, the plurality of word lines, and the plurality of insulating layers.