88results about How to "Timing error" patented technology

Methods and systems for processing and/or superimposing a medical image of an anatomical body (e.g., a heart) with graphical information are provided. Reference elements and/or reference catheter are placed in contact with the anatomical body. A physical structure within a navigational coordinate system is located using the reference elements and/or reference catheter. An image reference within an image coordinate corresponding to the physical structure is located. Location of the image reference can be accomplished, e.g., by displaying the medical image and electronically marking the displayed image reference, or by automatically locating image data corresponding to the image reference. The navigational and image coordinate systems are then registered based on the location of the physical structure within the navigational coordinate system and the location of the image reference within the image coordinate system, which allows graphical information to be accurately merged with the medical image data.

A method is disclosed for defining tracks on a rotating magnetic disk medium of a disk drive. Reference tracks are followed using a servo control loop while writing servo patterns defining a first target servo track. The servo control loop includes a two-dimensional digital state compensator having a first input that receives timing error signals, a first output that generates control signals for a controlled oscillator, a second output that generates timing state variables, and a second input that receives stored timing state variables. The first target track is followed using the servo control loop while servo patterns are written, and while the stored timing state variables corresponding to the servo patterns defining the first target track are applied to the second input.

A system and method for narrowing the range of frequency uncertainty of a Doppler shifted pilot signal in a satellite or other communications system with relative signal source and receiver motion. The satellite communications system includes a user terminal (for example, a mobile wireless telephone), a gateway (terrestrial base station), and at least one satellite with unknown position and unknown relative velocity. The method includes the steps of shifting the pilot signal over a plurality of frequency hypotheses, coherently accumulating samples of the pilot signal over a plurality of chips, measuring the energy of the accumulated pilot signal samples, accumulating the energy measurements over a plurality of chips to produce an energy accumulation value, and determining which of the plurality of frequency hypotheses results in the highest energy accumulation value.

A method and apparatus for transmitting/receiving a status report in a mobile communication system where Automatic Repeat reQuest (ARQ) and Hybrid Automatic Repeat reQuest (HARQ) operate together. An ARQ receiving (Rx) entity determines whether transmission of the status report is permitted, if a predetermined status report generation condition is satisfied. If the transmission of the status report is permitted, the ARQ Rx entity generates a status report depending on a reception status of ARQ packets received up to the time the transmission of the status report is permitted, and transmits the generated status report to an ARQ transmitting (Tx) entity through an allocated transmission resource. The ARQ Tx entity determines an initial reception time of an HARQ packet including the status report as a generation time of the status report, and performs retransmission according to the status report.

A method for handling video bitstream errors in a multimedia gateway device wherein a gateway device detects errors in the incoming video bitstream and sends a signal to the originating device to refresh the bitstream without need of error detection from an end terminating device. When the terminating device signals for the video bitstream to be refreshed, the gateway locally generates and transmits an appropriate refresh frame. The invention allows the gateway to handle errors for devices such as streaming and message servers that have no built-in error handling.

Methods and systems in a wireless receiver for enabling the reception of input signals at varied power levels in the presence of co-channel interference utilizing combinations of space-time adaptive processing (STAP), interference cancellation multi-user detection (MUD), and combined STAP/MUD techniques. In MUD, code, timing, and possibly channel information of multiple users are jointly used to better detect each individual user. The novel combination of adaptive signal reconstruction techniques with interference cancellation MUD techniques provides accurate temporal cancellation of interference with minimal interference residuals. Additional methods and systems extend adaptive signal reconstruction techniques to take Doppler spread into account. STAP techniques permit a wireless receiver to exploit multiple antenna elements to form beams in the direction of the desired signal and nulls in the direction of the interfering signals. The combined STAP-MUD methods and systems increase the probability of successful user detection by taking advantage of the benefits of each reception method. An additional method and system utilizes STAP techniques in the case where no pilot signal is available. This method compares the outputs of various hypothesized STAP solutions.

A method and system is disclosed for maintaining a communications protocol session between a client and server during times of inactivity at the client caused by other processing in the data path following a request by the client. For various client processes that may expire after a specified amount of inactivity during a particular session, an agent of the client in the data path can send a response containing illusory content to the client that causes the client to maintain the current session. The process at the client can ignore this illusory content response but, by processing it, the communications path session between the client and server can be maintained.

Disclosed is a hierarchical random access method for a wireless communication system having a significantly large cell. According to the present invention, a length of a preamble sequence and a length of a reference slot may be designed based on a terminal having greatest capacity of adjusting a timing error arrived at a base station, and a slot length may be designed to be an integer multiple of the length of the reference slot depending on a timing error correction capacity, thereby enabling terminals to use various slot lengths.

Limited-play optical medium with improved shelf stability are formed from a plurality of layers, including in sequence: (a) a first substrate layer; (b) a data layer; (c) a reflective layer; (d) a reactive layer comprising a dye having a reduced state and an oxidized state and further comprising an oxidized form of a reducing agent effective to convert the dye from the oxidized state to the reduced state, and (e) a second substrate layer. The dye in the reduced state is substantially transparent to light of wavelengths used to read the optical medium, and the dye in the oxidized state absorbs light of wavelengths used to read the optical medium. The reflective metal layer is formed from a metal or metal alloy that is not significantly oxidized by the oxidized form of the reducing agent. For example, the reflective metal layer is suitably formed from silver or gold.

The present application relates to a near field communications (NFC) receiver in which a received NFC signal comprising a carrier signal onto which a data signal is modulated is digitised and downconverted, and the digitised and downconverted received signal is filtered to recover a digitised and downconverted version of the carrier signal of the NFC signal. This digitised and downconverted version of the carrier signal is converted into an analogue signal which is then upconverted to generate an estimate of the carrier signal, and this estimate is combined with the received NFC signal to suppress or negate, at least partially, the carrier of the received signal.

A method for designing an integrated circuit such as a VLSI circuit, in particular optimizing delay of a signal transmitting through signal lines connecting a signal supplying source to each of elements, whereby skew can be decreased. The method can include determining whether the signal source satisfies a fan-out restriction if the signal source supplies a signal to all of the driven elements which are directly connected to the signal source, dividing the elements into groups so that the fan-out restriction is satisfied in each of the groups and each of the groups has the same or substantially same load capacity, when the signal source does not satisfy the fan-out restriction, and inserting into each group, a buffer having a size which makes the groups of elements satisfy the fan-out restriction. The dividing and the buffer inserting are repeated until a positive determination is delivered on the fan-out restriction.

A cascode current mirror circuit and a bandgap circuit are provided. The circuits are used together and function as a reference voltage circuit. The reference voltage circuit outputs a reference current resistant to temperature variation and ripple-voltage. Accordingly, a voltage stabilizing/regulating circuit corrects error voltage precisely and promptly, and the resultant voltage is temperature insensitive and ripple-voltage-independent.

A line capacitance is estimated in consideration of an influence of an adjacent line in rough routing, so that line paths can be determined so as to be free from a timing error. A routing graph is generated from a target integrated circuit, and line paths of cell-to-cell lines are initially determined on the basis of a passage cost set with regard to each of edges of the routing graph. With regard to each edge of the routing graph, the number of cell-to-cell lines passing through the edge is obtained as a line density, and a line capacitance of each line path in view of the influence of an adjacent line is estimated on the basis of the line density. It is verified whether or not there is a timing error with a delay time estimated, and when the integrated circuit does not satisfy a predetermined timing constraint, the line paths are re-determined with the passage cost of each edge allowed to be affected by the line capacitance. Alternatively, allocation to an interconnect layer is changed or a line-to-line distance is increased, so that the integrated circuit can satisfy the timing constraint.

A time-error-compensating apparatus and method corrects errors in a real-time clock caused by temperature fluctuations or other external influences. The apparatus includes a frequency counting unit which counts a high-frequency clock signal and a low-frequency clock signal, and a time compensating unit which computes a clock count compensation value based on a comparison of the count values of of the low-frequency and high-frequency clock signals. Correcting time using a high-frequency clock is highly desirable because a clock of this type has proven to be accurate in high external stress conditions. Use of this clock also allows the real-time clock to be implemented as a low-frequency, inexpensive low-frequency clock. The method and apparatus are well suited to correcting time information in the terminals of a mobile communications system, or in any other system or device where time tracking is sought.

The present invention provides a nonvolatile semiconductor memory device that can optimize a timing of performing an error detection and correction process to shorten a processing time. Upon receiving a write request to a memory cell array including a variable resistive element where information is stored based on a resistance state of a variable resistor, an input/output buffer outputs write data to a write control unit and an ECC control unit. The write control unit performs a data write process of writing divided data, obtained by dividing the write data into a predetermined number of data, to the databanks. The ECC control unit generates a first error correction code by performing an error correction code generation process to the write data or the divided data, in parallel with the data write process. The write control unit performs a code write process of writing first test data into an ECC bank.

A video signal processing apparatus is provided with a first clock generation circuit for generating a first clock synchronized with an input signal; a second clock generation circuit for receiving a set value to be a reference of an output frequency, adding the set value for every reference clock, extracting data according to the cumulative value, converting the data into an analog signal, reducing quantization noise, and multiplying the analog signal, thereby to obtain a second clock; and a clock switch circuit for generating a sync signal that is switched to the second clock, by using a sync signal generated with the first clock; and video signal processing is carried out using the second clock that is generated according to the resolution of a pixel display.