112 results about "Cascode current mirror" patented technology

A bias circuit for providing at least first and second bias signals for biasing a cascode current source and / or a cascode current sink includes a resistive element and first, second and third transistors, each transistor having first and second source / drain terminals and a gate terminal. The first source / drain terminal of the first transistor is coupled to the gate terminal, the first bias signal being generated at the first source / drain terminal in response to receiving a first reference current at the first source / drain terminal. A first end of the first resistive element is coupled to the second source / drain terminal of the first transistor. The gate terminal of the second transistor is coupled to the gate terminal of the first transistor, the second bias signal being generated at the first source / drain terminal of the second transistor in response to receiving a second reference current at the first source / drain terminal of the second transistor. The first source / drain terminal of the third transistor is coupled to the second source / drain terminal of the second transistor, the second source / drain terminal of the third transistor is coupled to a second end of the first resistive element, and the gate terminal of the third transistor is coupled to the first source / drain terminal of the second transistor.

A high-speed, low-noise charge pump for use in a phase-locked loop. The charge pump is constituted by first and second cascode current mirrors, as well as first and second switching transistors. The first cascode current mirror includes a first output mirror transistor and a first output cascode transistor. The first switching transistor is interposed between the first output mirror and the first output cascode transistors. During assertion of a first control signal, the first switching transistor is turned on so a first mirror current can flow through an output node. Likewise, the second cascode current mirror includes a second output mirror transistor and a second output cascode transistor. The second switching transistor is interposed between the second output mirror and the second output cascode transistors. During assertion of a second control signal, the second switching transistor is turned on so the second mirror current can flow through the output node.