544results about How to "Improve Noise Performance" patented technology

A circuit component built-in module includes: a first electrical insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a plurality of wiring patterns formed at least on a principal surface of the first electrical insulating substrate; a semiconductor chip incorporated in the first electrical insulating substrate and connected electrically with the wiring patterns; and inner vias electrically connecting the plurality of wiring patterns with one another, the inner vias passing through the first electrical insulating substrate. In the circuit component built-in module, the semiconductor chip has a thickness of not less than 30 mum and not more than 100 mum, and has a non-wired surface ground, and the circuit component built-in module has a thickness in a range of not less than 80 mum and not more than 200 mum. With this configuration, the high-performance and compact-size circuit component built-in module in which circuit components are mounted at a high density is provided so as to be used suitably in various types of electronic information devices.

An analog-to-digital converter system [50D] processing an input signal, g, which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal, d0(k), representing the sum of the input signal, g, and a dithering signal, y0. A digital-to-analog converter [156] generates an analog feedback signal, alpha, representing accurately the first digital signal, d0(k). The DAC [156] may be linearized by the use of mismatch-shaping techniques. A filter [158] generates the dithering signal, y0, by selectively amplifying in the signal band the residue signal, r0, defined as the difference of the input signal, g, and the analog feedback signal, alpha. Optional signal paths [166][168] are used to minimize the closed-loop signal transfer function from g to y0, which ideally will be zero. An analog compensation signal, m0, which is described by a well-controlled relationship to the residue signal, r0, is extracted from the filter [158]. Ideally, the closed-loop signal transfer function from g to m0 will be zero, or at least small in the signal band. A second quantizer [160] converts the analog compensation signal, m0, into a second digital signal, dm0(k). The two digital signals, d0(k) and dm0(k), are filtered individually and then added to form the overall output signal, dg(k). The second digital filter [164] has a low signal-band gain, which implies that the sensitivity to signal-band errors caused by the second quantizer [160] will be low. The output signal, dg(k), is a highly-accurate high-resolution representation of the input signal, g. Circuit imperfections, such as mismatch, gain errors, and nonlinearities, will cause only noise-like errors having a very low spectral power density in the signal band.The invention facilitates the implementation of uncalibrated highly-linear high-resolution wide-bandwidth A/D converters [50D], e.g., for use in digital communication systems, such as xDSL modems and other demanding consumer-market products for which low cost is of the essence.

A radiation imaging apparatus is capable of taking a moving picture by acquisition by a reading circuit of a plurality of radiation image signals on the basis of a plurality of successive times of irradiation of a radiation detector with radiation rays. The radiation detector has a two-dimensional array of pixels. In a period between a start of an n-th time of irradiation with radiation rays and a start of an (n+1)-th time of irradiation with radiation rays, where n is a natural number, a controller switches an operation status of an analog-to-digital converter that converts electric signals read by the reading circuit into digital signals so that power consumption of the analog-to-digital converter is reduced.

The invention discloses a shaftless driven type integrated motor propeller which is arranged on the tail part of a boat body of a water vehicle or underwater vehicle and comprises a front stator, a rotor propeller and a rear stator which are serially arranged on a solid non-rotating shaft, wherein the periphery of the propeller is connected with the circumferential rim of the annular propeller, a rotor permanent magnet is embedded in the circumferential rim of the propeller, a stator winding is arranged in the inner cavity of a guide pipe, the rotor permanent magnet and the stator winding are sealed by adopting water, and a gap is arranged between the rotor permanent magnet and the stator winding to form an annular motor. The rotor permanent magnet and the stator winding as well as the guide pipe are organically combined to form a modular unit, thus the shaftless driven type integrated motor propeller can be easily installed on a water platform or underwater platform, is suitable for large-power main propelling of a water boat or underwater submergible device, and has the advantages of reasonable structure, high propelling efficiency, low hydrodynamic force radiation noise, excellent cavitation property, safety and reliability.

A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency F_S and the chopping switches can operate at F_S or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.

A system and method for providing interleaving point-of-load (POL) regulators such that each regulator's switching cycle is phase displaced with respect to those of other POL regulators in the array is disclosed. As a result, the aggregate input and/or output reflected ripple and noise of the input, output, or both is reduced. Each regulator in the array is associated with an unique address. A serial data-line writes the phase spacing programmed to each addressable POL regulator in the array. The present invention permits phase displacement of POL regulators without limitation to the input and output voltages of each of the regulators in the array. The array of POL regulators may also operate in a phase displaced mode with only a single control line. The need for separate controllers and multiple control lines is thereby eliminated.

The invention discloses a low noise bandgap reference circuit and a reference source generation system. The reference source generation system comprises a bandgap reference generation circuit, a low dropout linear voltage stabilizing circuit and the low noise bandgap reference circuit. The low noise bandgap reference circuit comprises a starting circuit, a clamping circuit, a temperature coefficient compensation circuit and an output circuit, wherein the starting circuit is used for supplying starting voltage to other circuits and is turned off after other circuits are started; the clamping circuit comprises four metal oxide semiconductor (MOS) tubes which are connected by a current mirror structure to realize a clamping function; the temperature coefficient compensation circuit is used for performing temperature coefficient compensation on voltage which is output by the clamping circuit and generating reference voltage which is irrelevant to temperature; and the output circuit is used for outputting second reference voltage. The reference source generation system generates extremely low noise and has high power rejection ratios.

An integrator stage for use in a delta sigma modulator includes an operational amplifier, an integration capacitor coupling an output of the operational amplifier and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes first and second capacitors having first plates coupled electrically in common at a common plate node and switching circuitry for sampling selected reference voltages onto second plates of the capacitors during a sampling phase. The integrator stage further includes a switch for selectively coupling the common plate node and the summing node during an integration phase.

The invention discloses a low-power-consumption high-reliability electrification resetting circuit, and belongs to the field of integrated circuits. The low-power-consumption high-reliability electrification resetting circuit consists of a power supply detection circuit, a delay circuit and an exclusive OR circuit. A novel delay unit is used in the delay circuit, under the condition of not using the traditional large capacitor, the delay of hundreds of microseconds can be achieved, the area of a chip is effectively reduced, and the reliability of the chip is improved. The circuit has a full metal oxide semiconductor (MOS) tube structure, power supply noise is resisted by a phase inverter with a Schmidt function, and the static power consumption of the circuit is substantially zero after the circuit is reset.

A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Enhanced Cable Modem Termination System (CMTS) functionality, including programmable digital domain modulators and demodulators for dynamic channel assignment, is incorporated into Fiber Nodes (FNs) or mini Fiber Nodes (mFNs), yielding enhanced Fiber Nodes (eFNs). These eFns distribute CMTS functionality deep into Hybrid-Fiber-Coax Networks (HFCN) rather than centralizing the CMTS functions within a single location. Moving the cable modem terminations closer to the subscribers shortens the analog RF paths required to support cable modems. Communication of both subscriber data and CMTS control data is performed over Ethernet-compatible packet networks between the field-based CMTSs and an upstream facility (e.g., the Head End), which includes an Internet gateway. Packet data for multiple subscriber cable modems is easily compressed and merged over common network paths, reducing cabling plant complexity and increasing bandwidth utilization. This approach dramatically reduces the infrastructure cost per cable modem. Distributing CMTS functionality among multiple eFNs also reduces demands on already stretched resources at the Head End for space, power, and HVAC. For HFCN channels containing signals with modulation or encoding schemes that are unknown or best processed upstream, the invention also provides for tunneling their spectrum over the same packet network as used for the cable modem data. The channels to he tunneled are isolated using digital receivers, translated to baseband, their data framed, merged with cable modem subscriber data, and transmitted over the packet network. Upstream, the framed channel data is parsed and the original channel spectrum reconstructed to permit information recovery.