58results about How to "Improve ESD resistance" patented technology

The invention provides a liquid crystal display panel. According to the liquid crystal display panel, each test terminal at the periphery of an array substrate is provided with a switch circuit, when static electricity on the test terminals needs to be released through the switch circuits, all the test terminals are connected with a common electrode wire, and the static electricity is released through the common electrode wire, such that the anti-ESD capability of the test terminals is enhanced, and the service life of the liquid crystal display panel is prolonged.

The invention discloses an LDMOS SCR for protection against integrated circuit chip ESD protection and belongs to the technical field of electrons. According to the LDMOS SCR for the protection against the integrated circuit chip ESD, a low-voltage MOS is integrated on the basis of a traditional structure of the LDMOS SCR for the protection against the integrated circuit chip ESD and the low-voltage MOS is used for limiting a hole current injected from the positive electrode of the nested SCR, so that value of the holding voltage Vhold is improved and latch-up immune ability of the LDMOS SCR in high-voltage application is improved. In addition, compared with an ordinary LDMOS, the LDMOS SCR for the protection against the integrated circuit chip ESD is stronger in ability of the protection against the ESD due to the integrated SCR. Besides, the LDMOS SCR for the protection against the integrated circuit chip ESD and the Bipolar CMOS DMOS technology are compatible.

The invention discloses a light-emitting diode (LED) epitaxial structure and a manufacturing method thereof. The LED epitaxial structure successively comprises an epitaxial substrate, a leukotriene (LT)-GaN nucleating layer, a high-temperature non-doped buffer layer, a P-GaN layer, a P-AlGaN layer, a diffusion barrier layer, a multiple quantum well (MQW) luminous layer, an InGaN current expansion layer, an N-ZnO layer and a surface-coarsened ZnO layer. The manufacturing method comprises the following steps: pre-treating the epitaxial substrate; growing the nucleating layer; growing the buffer layer; growing the P-GaN layer; growing the P-AlGaN layer; growing the diffusion barrier layer; growing the MQW luminous layer; growing the InGaN current expansion layer; growing the N-ZnO layer; and growing the surface-coarsened ZnO layer. By using the LED epitaxial structure obtained by virtue of the manufacturing method provided by the invention, an excellent electrical property and a good optical property are obtained, the internal quantum efficiency and the electronic static discharge (ESD) resistance capability are improved, the lost light caused by total reflection is lowered, the external quantum efficiency is greatly improved, a high-brightness LED is obtained, and the purposes of development and sustainable development of the LED industry are greatly promoted.

The invention relates to an LED (Light-Emitting Diode) epitaxial wafer and a growing method thereof, wherein the LED epitaxial wafer comprises two p-type GaN layers, and the growing method of the LED epitaxial wafer comprises the following steps of: when the p-type GaN layers grow, firstly growing a first p-type GaN layer at lower temperature and under lower pressure, and then growing a second p-type GaN layer when the temperature is relatively higher. Because the growing temperature of the first p-type GaN layer is low, an irregular structure is formed behind a quantum well to enable static electricity to be easily dispersed, so that the anti-ESD (Electro-Static discharge) capability of a GaN-based LED chip is improved. The invention has the advantages that the anti-ESD capability of the GaN-based LED chip is improved, the 2000V ESD passing rate of the chip with the size of 300*300mu m<2> can reach 98 percent, and the 4000V ESD passing rate can reach 95 percent.

The invention discloses a multi-porous channel current equalizing-based transient voltage suppressor, which comprises a P+ substrate layer and a P- epitaxial layer. An N+ buried layer is arranged between first epitaxial regions and the P+ substrate layer; second epitaxial regions are respectively provided with N+ active injection regions; N wells are respectively embedded on the first epitaxial regions; each N well is provided with a P+ active injection region; the P+ active injection regions are connected with the N+ active injection regions through metal electrodes; the N wells are connected with the N+ active injection regions respectively paved on the first epitaxial regions; and the N+ active injection regions are connected with the N+ buried layer through a plurality of porous channels in which N-type materials are respectively filled. According to the multi-porous channel current equalizing-based transient voltage suppressor disclosed by the invention, electronic static discharge (ESD) current is evenly lead to Zener junctionby adopting the multi-porous channel current equalizing technology, so that the current collected by the Zener nodes is basically the same in density, and thereby, the phenomenon that the partial failure the Zener nodes is caused because of different current densities is avoided, the area utilization ratio of the node is effectively increased, meanwhile, the on resistance is lowered, the clamping feature is improved, and the ESD resistance of devices is enhanced.

A portable information processing device includes a circuit board portion that has a main body portion side board mounting an electronic circuit thereon and forming a main body portion, and a connector portion side board forming a connector portion for connection to electronic equipment, wherein the main body portion side board mounts an electronic circuit on at least one of a first surface and a second surface opposite to the first surface, and is provided with a main body portion side electro-static discharge line which functions as an electro-static discharge surge arrester at an edge portion of a surface on which at least an electronic circuit is mounted, and wherein the connector portion side board is provided with a connector portion side electro-static discharge line which is connected to the main body portion side electro-static discharge line and functions as an electro-static emission portion. According to the portable information processing device, ESD resistance.

The invention provides a touch substrate, a manufacture method thereof, and a touch screen, and belongs to the technical field of touch. The touch substrate comprises a touch area and a black matrix graph which surrounds the touch area; the touch substrate is provided with a plurality of touch electrodes, wherein a virtual electrode graph is formed in each gap between the adjacent touch electrodes; and each virtual electrode graph overlapped between the touch electrodes on the black matrix graph consists of a plurality of mutually-insulated virtual electrode blocks.

The invention provides a liquid crystal display panel. The panel comprises an array substrate, a color film substrate, a liquid crystal layer and bezel glue, after the two substrates are assembled, adisplay area and a non-display area are correspondingly formed, the liquid crystal is located between the two substrates, and a closed area enclosed by the bezel glue is filled with the liquid crystallayer; at least two first metal lines are formed on the non-display area of the array substrate and used for shielding leakage light of a BM groove formed in the side, close to the liquid crystal layer, of the non-display area of the color film substrate; the array substrate further comprises a shading plate, the shading plate is arranged in the non-display area of the array substrate and locatedbelow the two first metal lines, and the length of the shading plate is greater than or equal to the spacing between the two first metal lines to eliminate the phenomenon of edge red lines occurringon the BM groove. By utilizing the liquid crystal display panel, the shading plate is additionally arranged in the non-display area of the array substrate and located below the metal lines used for shielding the leakage light of the BM groove of the color film substrate to eliminate the phenomenon of edge red lines, and the product yield is improved.

The invention relates to the technical field of semiconductors and discloses a resistance structure for improving a silicon-on-insulator (SOI) circuit ESD protection network. By using the conductor characteristics of silicide, the structure solves the problem that a semiconductor current carrier conducting resistance structure enables resistance not to reduce the resistance value and the potential lifting capability of resistance but increase the resistance value and improve the potential lifting capability of the resistance in a large-scale ESD process at high temperature because of the characteristics of the resistance negative temperature generated by the intrinsic ionization effect. In addition, the resistance also has the stable resistance value characteristics after ESD, the problem of the impurity tempering effect generated in the ESD process of the semiconductor current carrier conducting resistance is solved, and the effect on electrical properties of a circuit is further reduced. By using the invention, on one hand, more stable ESD protecting capability can be obtained, on the other hand, the effect on the electrical properties of a circuit by the resistance for protecting the ESD can be reduced when more stable ESD protecting capability is obtained.

Embodiments of the invention provide a display apparatus and a manufacturing method therefor. The manufacturing method comprises the steps of attaching a static shielding layer to an edge region of a connecting line pattern, wherein the connecting line pattern is exposed on a display panel; the static shielding layer is provided with an insulating material region; the insulating material region is in contact with the region where the connecting line pattern is located; and the other region, except the region where the connecting line pattern is located, in the edge region is in contact with a conductive material region on the surface of the static shielding layer. The display apparatus provided by the embodiments of the invention is prepared by the manufacturing method; the anti-ESD (electrostatic discharge) capability of the chip connecting line position on the edge can be improved without increasing technological processes; in addition, the formed material, including the metal static shielding layer, is non-transparent; compared with a photo-sensitive resist, the surface attaching condition of the static shielding layer is easier to detect, and surface flatness defects cannot be formed easily; and the yield and improvement of the performance of the product can be facilitated.

The embodiment of the invention relates to a touch sensor and a production method thereof, and a touch panel. The touch sensor comprises a base plate, an electrode layer, a first insulating layer and a transparent conductive layer, wherein the electrode layer is arranged on the base plate, wherein the electrode layer consists of a first electrode and a second electrode which are isolated from each other; the first insulating layer is arranged on the electrode layer; the transparent conductive layer is arranged on the first insulating layer, wherein the transparent conductive layer consists of a bridging part and an ESD protective part, the bridging part is arranged to be bridged with the first electrode or the second electrode, and the ESD protective part is isolated from the bridging part. According to the touch sensor provided by the embodiment of the invention, the antistatic capability of a functional layer inside the sensor can be improved.

The invention discloses an SGT MOSFET device with bidirectional ESD protection capability, which comprises a cellular structure, and is characterized in that the cellular structure comprises drain metal, an N + substrate, an N-type drift region and source metal which are stacked in sequence from bottom to top; a trench gate structure is formed on one side of the upper surface of the N-type drift region, and the trench gate structure comprises an N + Poly gate, a P-type lightly doped region I, an N-type lightly doped region, a P-type lightly doped region II and an N-type source contact region which are sequentially arranged from top to bottom. On the basis of a traditional SGT MOSFET structure and a polycrystalline silicon multi-doped longitudinal MOSFET structure, the switching performanceand the ESD protection performance of the power MOS device are improved at the same time.

The invention provides a touch substrate, a manufacturing method of the touch substrate and a touch screen, and belongs to the technical field of touch. The touch substrate comprises a touch area and a black matrix graphic which encircles the touch area; a plurality of touch electrode graphics are arranged on the touch substrate; each touch electrode graphic comprises a first part which is overlapped on the black matrix graphic; and the included angle between any two adjacent edges of each first part is greater than a preset threshold value. According to the technical scheme of the invention, the anti-ESD ability of the touch screen can be improved.

Provided are a touch panel and a touch display device provided with the same. The touch panel comprises a touch region and a wiring region located on the periphery of the touch region and surrounding the touch region. The wiring region comprises various conductive signal wires required by the touch panel, at least one starved inspection reference line is arranged in the wiring region, formed by arranging multiple metal blocks at intervals, located on the outer sides of the conductive signal wires in the wiring regions and used in the bonding manufacture process of the display device using the touch panel, and inspectors can conveniently perform starvation inspection by means of a method for inspecting whether optical cement covers the starved inspection reference line or not. The touch panel is provided with one starved inspection reference line in the wiring region, so that the inspectors can conveniently and quickly perform starvation inspection in the bonding manufacture process of the touch panel and a glass cover plate of the touch display device.

The invention provides a method for improving an ESD protective capability of an SOI NMOS device and the SOI NMOS device. The method for improving the ESD protective capability of the SOI NMOS device comprises: carrying out well region ion injection and channel ion injection in a silicon top layer of SOI to form a device area; forming a gate oxide layer at the top of the device area; forming a gate structure containing gate side walls on the gate oxide layer through deposition and etching; arranging a photoresist layer on the exposed silicon top layer surface and device area surface and partially removing the photoresist layer from the device area surface so as to partially expose the device area surface; carrying out partial inclined injection by using the photoresist layer to form a partial ESD ion injection area in the device area; and respectively forming a drain electrode and a source electrode in the device area on two sides of the gate structure.