117results about How to "High Power Handling Capability" patented technology

A method of fabricating AlGaN / GaN enhancement-mode heterostructure field-effect transistors (HFET) using fluorine-based plasma immersion or ion implantation. The method includes: 1) generating gate patterns; 2) exposing the AlGaN / GaN heterostructure in the gate region to fluorine-based plasma treatment with photoresist as the treatment mask in a self-aligned manner; 3) depositing the gate metal to the plasma treated AlGaN / GaN heterostructure surface; 4) lifting off the metal except the gate electrode; and 5) high temperature post-gate annealing of the sample. This method can be used to shift the threshold voltage of a HFET toward a more positive value, and ultimately convert a depletion-mode HFET to an enhancement-mode HFET (E-HFET).

A SAW filter includes a piezoelectric substrate of Lithium Niobate or optionally Lithium Tantalate having a thickness of at least twice an acoustic wavelength. The piezoelectric substrate is bonded to a surrogate substrate of a silicon material. The surrogate substrate is characterized by a resisitivity of at least 100 ohm-cm and an expansion coefficient compatible with the piezoelectric substrate. A catalytic bonding film between the piezoelectric substrate and the surrogate substrate is formed from a first catalytic bonding film deposited onto a surface of the piezoelectric substrate and a second catalytic bonding film deposited onto a surface of the surrogate substrate. The piezoelectric substrate is bonded to the surrogate substrate through a compression force sufficient for providing a bonding at a normal temperature.

A SAW filter includes a piezoelectric substrate of Lithium Niobate or optionally Lithium Tantalate having a thickness of at least twice an acoustic wavelength. The piezoelectric substrate is bonded to a surrogate substrate of a silicon material. The surrogate substrate is characterized by a resisitivity of at least 100 ohm-cm and an expansion coefficient compatible with the piezoelectric substrate. A catalytic bonding film between the piezoelectric substrate and the surrogate substrate is formed from a first catalytic bonding film deposited onto a surface of the piezoelectric substrate and a second catalytic bonding film deposited onto a surface of the surrogate substrate. The piezoelectric substrate is bonded to the surrogate substrate through a compression force sufficient for providing a bonding at a normal temperature.

A tunable transmissive grating comprises a transmissive dispersive element, a reflective element, and an angle θ formed between the two elements. A first optical path is formed according to the angle θ, wherein light dispersing from the dispersive element is directed onto the reflective element and reflects therefrom. At least one element is rotatable about a rotational center to cause a second optical path and thereby tune the wavelength of the light reflecting from the reflective element. Both elements can be rotatable together around a common rotational center point according to certain embodiments, and / or each element can be independently rotated around a rotational axis associated only with that element. According to some embodiments, the relative angle θ formed between the elements is held constant; however, in other embodiments θ can vary.

A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN / GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma treatment and high temperature post-gate annealing of the sample. Device isolation is achieved by either mesa etching or fluoride-based plasma treatment. This method provides a complete planar process for GaN-based integrated circuits favored in high-density and high-speed applications.

A method of fabricating AlGaN / GaN enhancement-mode heterostructure field-effect transistors (HFET) using fluorine-based plasma immersion or ion implantation. The method includes: 1) generating gate patterns; 2) exposing the AlGaN / GaN heterostructure in the gate region to fluorine-based plasma treatment with photoresist as the treatment mask in a self-aligned manner; 3) depositing the gate metal to the plasma treated AlGaN / GaN heterostructure surface; 4) lifting off the metal except the gate electrode; and 5) high temperature post-gate annealing of the sample. This method can be used to shift the threshold voltage of a HFET toward a more positive value, and ultimately convert a depletion-mode HFET to an enhancement-mode HFET (E-HFET).

In an array of single crystal acoustic resonators, the effective coupling coefficient of first and second strained single crystal filters are individually tailored in order to achieve desired frequency responses. In a duplexer embodiment, the effective coupling coefficient of a transmit band-pass filter is lower than the effective coupling coefficient of a receive band-pass filter of the same duplexer. The coefficients can be tailored by varying the ratio of the thickness of a piezoelectric layer to the total thickness of electrode layers or by forming a capacitor in parallel with an acoustic resonator within the filter for which the effective coupling coefficient is to be degraded. Further, a strained piezoelectric layer can be formed overlying a nucleation layer characterized by initial surface etching and piezoelectric layer deposition parameters being configured to modulate a strain condition in the strained piezoelectric layer to adjust piezoelectric properties for improved performance in specific applications.

Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SP4T switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz and 1.9 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate tuning to block high power signals from the transmit path as well as to maintain low insertion loss at the receiver path. On the other hand, in the transmit switch, a body substrate tuning technique may be applied to maintain high power delivery to the antenna. Example embodiments of the CMOS antenna switch may provide for 31 dBm P 1 dB at both bands (e.g., 900 MHz and 1.8 GHz). In addition, a 0.9 dB and −1.1 dB insertion loss at 900 MHz and 1.9 GHz, respectively, may be obtained according to example embodiments of the invention.

A high power high temperature superconductive circuit for use in various microwave devices including filters, dielectric resonator filters, multiplexers, transmission lines, delay lines, hybrids and beam-forming networks has thin gold films deposited either on a substrate or on top of the high temperature superconductive film. Alternatively, other metal films can be used or a plurality of dielectric films can be used or a dielectric constant gradient substrate can be used. The use of these materials in a part or parts of a microwave circuit reduces the current density in those parts compared to the level of current density if only high temperature superconductive film is used. This increases the power handling capability of the circuit.

An in-line capacitor, having a pair of inner conductor segments, each of the inner conductor segments having a mating surface. A dielectric spacer positioned between the mating surfaces, each of the mating surfaces having corresponding folds formed thereon.

A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN / GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma treatment and high temperature post-gate annealing of the sample. Device isolation is achieved by either mesa etching or fluoride-based plasma treatment. This method provides a complete planar process for GaN-based integrated circuits favored in high-density and high-speed applications.

A power over Ethernet controller supporting a plurality of powering modes, the power over Ethernet controller comprising: a pair of power sourcing equipments; and a control circuit; the control circuit being operative to control each of the pair of power sourcing equipment units in one of a first mode and a second mode, the first mode comprising operating the pair of power sourcing equipments as a single power sourcing equipment operable to power a single powered device over communication cabling, and the second mode comprising operating each of the power sourcing equipments of the pair independently so as to each be operable to power an associated powered device over communication cabling.

Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and source and body connection along with body floating technique to block high power signals from the transmit path by preventing channel formation of the device in OFF state as well as to maintain low insertion loss at the receiver path. Example embodiments of the CMOS antenna switch may provide for 35 dBm P 1 dB at both bands (e.g., 900 MHz and 1.9 GHz and 2.1 GHz). In addition, a −60 dBc second and third harmonic up to 28 dBm input power to the switch, may be obtained according to example embodiments of the invention.

Method for synchronizing inverter units (INU11, INU12) that are connected in parallel and supply a motor, and a parallel connection arrangement, in which motor is either one winding, which is supplied by inverter units connected in parallel, or a plurality of parallel windings, in which each winding is supplied by its own inverter unit, in which parallel connection one inverter unit functions as a master and the others as slaves, in which method a telecommunications bus is arranged between the units, and in which each inverter unit has its own modulation cycle counter, which are synchronized with each other on the basis of telecommunications messages, preferably serial telecommunications messages. In the invention all the inverter units take into memory the value of their own modulation counter at the termination time of a telecommunications message (Mes2), the master inverter unit sends the reading of its own counter in the following message to the other inverter units, and the other inverter units correct the reading notified by the master on the basis of the readings of their own modulation counters in the direction that makes the counters operate as simultaneously as possible.

A single trigger / shunt coil is utilized for combined induced magnetic field triggering and shunt impedance. The single coil connected in parallel with the high temperature superconducting element, is designed to generate a circulating current in the parallel circuit during normal operation to aid triggering the high temperature superconducting element to quench in the event of a fault. The circulating current is generated by an induced voltage in the coil, when the system current flows through the high temperature superconducting element.

The present invention is directed to a coupler that includes a coupler structure including at least one first transmission line disposed on a first major surface of a coupler dielectric substrate and at least one second transmission line disposed on a second major surface of the coupler dielectric substrate. The coupler structure includes four symmetric ports such that each port of the four symmetric ports is characterized by substantially identical impedance characteristics. A first ground plane structure is coupled to the coupler structure and including a first outer dielectric material and a first conductive exterior layer disposed substantially parallel to the first major surface. A second ground plane structure is coupled to the coupler structure and including a second outer dielectric material and a second conductive exterior layer disposed substantially parallel to the second major surface. A thermal path is disposed between the coupler structure and at least one of the first conductive exterior layer or second conductive exterior layer. The thermal path is characterized by a thermal resistance substantially within a range between 15 W / mK and 50 W / mK, such that the coupler has a power handling capability of more than 800 W per square inch of heat sink interface.

A waveguide orthomode transducer. In a first layer a turnstile junction having a main waveguide and four waveguide ports, and four hybrid tees each have an e-port, two opposed side-ports, and an h-port. The hybrid tees are ring-arranged around the turnstile junction so the waveguide ports each communicate with one h-port, so adjacent hybrid tees inter communicate with their respective side-ports, and so the e-ports form two sets of opposed e-ports. In a second layer two h-plane power dividers / combiners each have an axial-port and two opposed side-ports. The h-plane power dividers / combiners are arranged so their respective side-ports communicate with different ones of the two sets of opposed e-ports and so their axial-ports are polarization ports. This permits a single signal with two fundamental orthogonally polarized modes to enter the main waveguide and exit separated at the polarization ports vice versa.

A power electronic device package comprising a base member, a device layer, multiple leads, and an encapsulant is provided. The base member is thermally conductive for heat dissipation. The device layer comprises one or more power electronic devices mounted on the base member. The power electronic devices are selectively electrically connected to each other and to the base member to form an internal electronic circuit. The leads extend outwardly from the base member and are electrically connected to the internal electronic circuit. The encapsulant encases the internal electronic circuit, a portion of the base member, and a portion of the leads. The power electronic device package is configured as a transfer molded power module with multiple leads and increased power handling capability. In an embodiment, the base member is electrically conductive to operate as an electrical terminal. The base member may also be isolatably connected to the internal electronic circuit.

The present invention improves the geometry of ferrite circulators in order to increase the average power handling by decreasing the temperature rise in the ferrite and associated adhesive bonds. Embodiments of the present invention utilize dielectric attachments on the sides of the ferrite element, which maximizes the area of contact and minimizes the path length from the ferrite element out to the thermally conductive attachments.

A SAW filter includes a piezoelectric substrate of Lithium Niobate or optionally Lithium Tantalate having a thickness of at least twice an acoustic wavelength. The piezoelectric substrate is bonded to a surrogate substrate of a silicon material. The surrogate substrate is characterized by a resisitivity of at least 100 ohm-cm and an expansion coefficient compatible with the piezoelectric substrate. A catalytic bonding film between the piezoelectric substrate and the surrogate substrate is formed from a first catalytic bonding film deposited onto a surface of the piezoelectric substrate and a second catalytic bonding film deposited onto a surface of the surrogate substrate. The piezoelectric substrate is bonded to the surrogate substrate through a compression force sufficient for providing a bonding at a normal temperature.

An embodiment of the present invention provides an apparatus, comprising a frequency agile, directive patch antenna in a phased array with frequency agile elements, wherein the directive patch antenna is capable of generating a main radiation beam that is capable of being steered using electronically controlled phased shifters and wherein at least one tunable capacitors controls the resonant response of individual antenna elements within the phased array.

A radar level gauge system is disclosed, having a transmitter for transmitting measuring signals towards the surface of the filling material, a receiver for receiving echo signals from said surface and a fastening structure adapted to secure said transmitter and receiver in a measuring position on a feed-through structure located in an upper boundary of said container. Further, a sealing unit is arranged between said fastening structure and said feed-through, and adapted to provide a pressure seal between the inside and the outside of the container, and in addition, there is provided means for blocking electromagnetic energy, adapted to block net transfer of electromagnetic energy between the inside and the outside of the container through said sealing unit.

A dynamic braking circuit for an electronic motor drive shunts the DC link of the drive with a resistor using two control strategies. The first control strategy used for lower levels of braking employs a pulse width modulated signal and the second control strategy used for higher levels of braking uses a hysteretic signal significantly reducing switching losses in the semiconductor devices controlling the dynamic braking resistor allowing higher braking capacity.

Method for synchronizing inverter units (INU11, INU12) that are connected in parallel and supply a motor, and a parallel connection arrangement, in which motor is either one winding, which is supplied by inverter units connected in parallel, or a plurality of parallel windings, in which each winding is supplied by its own inverter unit, in which parallel connection one inverter unit functions as a master and the others as slaves, in which method a telecommunications bus is arranged between the units, and in which each inverter unit has its own modulation cycle counter, which are synchronized with each other on the basis of telecommunications messages, preferably serial telecommunications messages. In the invention all the inverter units take into memory the value of their own modulation counter at the termination time of a telecommunications message (Mes2), the master inverter unit sends the reading of its own counter in the following message to the other inverter units, and the other inverter units correct the reading notified by the master on the basis of the readings of their own modulation counters in the direction that makes the counters operate as simultaneously as possible.

A thin-film, radio frequency terminator is provided that includes a mounting flange and a thin-film termination chip mounted on a surface of the mounting flange. The mounting flange grounds the termination chip. The termination chip includes a substrate, a terminal, a metallization layer including a resistor pad electrically connecting the terminal to the mounting flange, and a cover. The terminator has a low physical profile but provides high power handling capability.

Embodiments of the invention may provide for a CMOS antenna switch, which may be referred to as a CMOS SPDT switch. The CMOS antenna switch may operate at a plurality of frequencies, perhaps around 900 MHz 1.9 GHz and 2.1 GHz according to an embodiment of the invention. The CMOS antenna switch may include both a receiver switch and a transmit switch. The receiver switch may utilize a multi-stack transistor with body substrate switching and source and body connection along with body floating technique to block high power signals from the transmit path by preventing channel formation of the device in OFF state as well as to maintain low insertion loss at the receiver path. Example embodiments of the CMOS antenna switch may provide for 35 dBm P 1 dB at both bands (e.g., 900 MHz and 1.9 GHz and 2.1 GHz). In addition, a −60 dBc second and third harmonic up to 28 dBm input power to the switch, may be obtained according to example embodiments of the invention.

A three element antenna utilizes a truncated parabolic reflector dish of diameter "d" and focal point "f" and a director plate for receiving and transmitting high frequency signals in conjunction with a substantially horizontal conducting ground plane. The antenna is mounted to a planar transverse end wall, defining the lower truncated end of the parabolic surface, and the antenna elements are proximate to the focal point "f" of the paraboloid that defines the dish. The director plate is positioned at the opening (defining the diameter "d"), is distal to the focal point and the antenna elements, and positions an array of director rods about the antenna elements to focus signals relative to the parabolic surface. The ratio of (f / d) is about 0.01 to about 0.625, and preferably about 0.210.

The present invention improves the geometry of ferrite circulators in order to increase the average power handling by decreasing the temperature rise in the ferrite and associated adhesive bonds. Embodiments of the present invention utilize dielectric attachments on the sides of the ferrite element, which maximizes the area of contact and minimizes the path length from the ferrite element out to the thermally conductive attachments.