30results about How to "Achieve low power consumption" patented technology

The pesent invention provides a source driver capable of reducing power consumption accompanying conversion operation of a level shifter in accordance with the driving mode, to provide an electro-optical device including the source driver and to provide electronic equipment. The source driver 520 comprises a drive mode setting register 690 for setting the source driver to normal drive mode or power saving drive mode, first to sixth level shifters LST1to LST6for converting the amplitude of each bit signal of 6 bits-display data, an operational amplifier OPAMP1for driving a source line based on a gradation voltage corresponding to an output signal of the first to sixth level shifters LST1to LST6in the normal drive mode and a voltage setting circuit VSET1for setting a voltage corresponding to uppermost bit data of the display data to an output of the operational amplifier OPAMP1in the power saving drive mode. In the power saving drive mode, only an input signal of the first to fifth level shifters LST1to LST5is fixed.

A semiconductor memory device includes a plurality of memory blocks, a plurality of refresh block counters, a refresh word line counter, and an arbitration circuit. The plurality of refresh block counters generate block addresses of at least two memory blocks to select at least two memory blocks to be refreshed from the plurality of memory blocks. The refresh word line counter generates a common word line address that is common to the at least two memory blocks. The arbitration circuit generates at least one first word line address based on the at least two block addresses and the common word line address and arbitrate so that each word line indicated by the at least one first word line address is refreshed during a period in which a word line indicated by an externally applied second word line address is accessed.

The present invention aims to providing a method for determining design values for a quartz oscillating circuit, through using a relation of load capacitance CL, negative resistance RL and drive current Ios of the oscillating circuit of a quartz oscillator. The third value can be determined through using a relation formula or a relation curve after determining two values of the negative resistance RL, the load capacitance CL and the drive current Ios, in the process of using the quartz oscillating circuit of the quartz oscillator.

A reference voltage generation circuit for driving a liquid crystal display comprises a positive polarity ladder resistor circuit including a first ladder resistor circuit (212) between first and second power source lines supplied with first and second power source voltages (VDD, VSS), respectively, and a negative polarity ladder resistor circuit including a second ladder resistor circuit (222) between the first and second power source lines. First to i-th reference voltage output switching circuits (VSW1-VSWi) are respectively inserted between first to i-th division nodes (ND 1 -ND i ) of the first ladder resistor circuit (212), where i is an integer larger than or equal to 2, and first to i-th reference voltage output nodes (VND 1 -VND i ). (i + 1)th to 2i-th reference voltage output switching circuits (VSW(i+1)-VSW2i) are respectively inserted between (i + 1)th to 2i-th division nodes (ND i+1 -ND 2i ) of the second ladder resistor circuit and the first to i-th reference voltage output nodes. When polarity inversion of a voltage outputted by a polarity inversion drive system at a given polarity inversion period is repeated, the first to i-th reference voltage output switching circuits are switched on during a positive polarity driving period and switched off during a negative polarity driving period; and the (i + 1)th to 2i-th reference voltage output switching circuits are switched off during the positive polarity driving period and switched on during the negative polarity driving period.

This invention implements a shift register, for driving a scanning-signal line, that makes it possible to reduce the bezel width and power consumption of a display device while ensuring reliability over long-term operation. In each of a number of stages, an output-control-node stabilization section (420) of a circuit constituting that stage comprises the following: a thin-film transistor (M5) wherein a fourth clock (CKD) that changes from an OFF level to an ON level when a scanning signal outputted by the previous stage is to change from an OFF level to an ON level is supplied to the gate terminal, the drain terminal is connected to an output-control node (NA), and the scanning signal outputted by the previous stage is supplied to the source terminal; and a thin-film transistor (M6) wherein a third clock (CKC) that changes from an OFF level to an ON level when a scanning signal outputted by the next stage is to change from an OFF level to an ON level is supplied to the gate terminal, the drain terminal is connected to the aforementioned output-control node (NA), and the scanning signal outputted by the next stage is supplied to the source terminal.