30results about How to "Achieve low power consumption" patented technology

The pesent invention provides a source driver capable of reducing power consumption accompanying conversion operation of a level shifter in accordance with the driving mode, to provide an electro-optical device including the source driver and to provide electronic equipment. The source driver 520 comprises a drive mode setting register 690 for setting the source driver to normal drive mode or power saving drive mode, first to sixth level shifters LST1to LST6for converting the amplitude of each bit signal of 6 bits-display data, an operational amplifier OPAMP1for driving a source line based on a gradation voltage corresponding to an output signal of the first to sixth level shifters LST1to LST6in the normal drive mode and a voltage setting circuit VSET1for setting a voltage corresponding to uppermost bit data of the display data to an output of the operational amplifier OPAMP1in the power saving drive mode. In the power saving drive mode, only an input signal of the first to fifth level shifters LST1to LST5is fixed.

A semiconductor memory device includes a plurality of memory blocks, a plurality of refresh block counters, a refresh word line counter, and an arbitration circuit. The plurality of refresh block counters generate block addresses of at least two memory blocks to select at least two memory blocks to be refreshed from the plurality of memory blocks. The refresh word line counter generates a common word line address that is common to the at least two memory blocks. The arbitration circuit generates at least one first word line address based on the at least two block addresses and the common word line address and arbitrate so that each word line indicated by the at least one first word line address is refreshed during a period in which a word line indicated by an externally applied second word line address is accessed.

There is provided an oscillation circuit using a crystal vibrator including means A for obtaining an oscillation activation time Ts (Ts0) from an oscillation margin M by using a relational equation between the oscillation activation time Ts and the oscillation margin M or a relational graph thereof; means B for obtaining a relational equation between the oscillation activation time Ts and a load capacitance CL in an arbitrary driving current value Ios from the relational equation between the oscillation activation time Ts and the load capacitance CL, and the driving current value Ios; and means C for determining the load capacitance CL corresponding to the oscillation activation time Ts0 obtained by the means A, by using the relational equation between the oscillation activation time Ts and the load capacitance CL, which is obtained by the means B.

Provided is a semiconductor integrated circuit device which enables reduction is power consumption. The semiconductor integrated circuit device has a circuit block 1C including a plurality of components 101e to 120e, and a voltage of a value different from those of other components is supplied to at least one of the plurality of components 101e to 120e from electric sources 11 to 14 which supply voltages VDD1 to VDD4.

The present invention aims to providing a method for determining design values for a quartz oscillating circuit, through using a relation of load capacitance CL, negative resistance RL and drive current Ios of the oscillating circuit of a quartz oscillator. The third value can be determined through using a relation formula or a relation curve after determining two values of the negative resistance RL, the load capacitance CL and the drive current Ios, in the process of using the quartz oscillating circuit of the quartz oscillator.

There is provided an oscillation circuit including a crystal vibrator that is connected between input and output terminals of a CMOS inverter making up the oscillation circuit; an input wiring line that includes a crystal vibrator-side input terminal connected to an input terminal pad of the CMOS inverter; an output wiring line that includes a crystal vibrator-side output terminal connected to an output terminal pad of the CMOS inverter; a ground power source wiring line that includes a crystal vibrator-side ground power source terminal; and a capacitative element that is connected between the input wiring line and the ground power source wiring line, and between the output wiring line and the ground power source wiring line, wherein the ground power source wiring line is disposed at least a part of between the input wiring line and the output wiring line.

A reference voltage generation circuit for driving a liquid crystal display comprises a positive polarity ladder resistor circuit including a first ladder resistor circuit (212) between first and second power source lines supplied with first and second power source voltages (VDD, VSS), respectively, and a negative polarity ladder resistor circuit including a second ladder resistor circuit (222) between the first and second power source lines. First to i-th reference voltage output switching circuits (VSW1-VSWi) are respectively inserted between first to i-th division nodes (ND 1 -ND i ) of the first ladder resistor circuit (212), where i is an integer larger than or equal to 2, and first to i-th reference voltage output nodes (VND 1 -VND i ). (i + 1)th to 2i-th reference voltage output switching circuits (VSW(i+1)-VSW2i) are respectively inserted between (i + 1)th to 2i-th division nodes (ND i+1 -ND 2i ) of the second ladder resistor circuit and the first to i-th reference voltage output nodes. When polarity inversion of a voltage outputted by a polarity inversion drive system at a given polarity inversion period is repeated, the first to i-th reference voltage output switching circuits are switched on during a positive polarity driving period and switched off during a negative polarity driving period; and the (i + 1)th to 2i-th reference voltage output switching circuits are switched off during the positive polarity driving period and switched on during the negative polarity driving period.

The invention discloses a buoyancy-driven intelligent self-lifting communication subsurface buoy system which comprises an intelligent self-lifting communication floating body, a main floating body and an anchoring system. The intelligent self-lifting communication floating body comprises a main frame, a floating body material, a communication antenna, an electronic compartment, a battery compartment, an acoustic module and a buoyancy-driven adjusting mechanism. The buoyancy-driven intelligent self-lifting communication subsurface buoy system has the advantages that the subsurface buoy system can realize real-time transmission of data of a subsurface buoy, so that timeliness of the data is guaranteed; switching of a working state of a mechanism around a density jumping layer is realized by cooperation of the buoyancy-driven adjusting mechanism and a control system, long-term working capability of the surface buoy system at low power consumption is realized, floating motion and a communication function under low ocean current are realized, overall power consumption of the subsurface buoy system is lowered, and working cycle of the subsurface buoy system is prolonged greatly; by being controlled to float and dive, the communication subsurface buoy is effectively protected from being damaged by organisms or ships on the sea, and high working reliability of the subsurface buoy is guaranteed.

In the prior art, in a conveyor line in which conveyor lines driven in different directions are arranged in multiple layers, it is necessary to provide the same number of power sources for driving the conveyor belts of each conveyor line as the number of conveyor lines. Therefore, the number of driving sources increases, and the power consumption of the entire device inevitably increases. The present invention adopts a mechanism for driving a plurality of conveying lines in parallel by one power source, thereby reducing the number of power sources required for driving the conveying lines and realizing low power consumption of the system.

This invention implements a shift register, for driving a scanning-signal line, that makes it possible to reduce the bezel width and power consumption of a display device while ensuring reliability over long-term operation. In each of a number of stages, an output-control-node stabilization section (420) of a circuit constituting that stage comprises the following: a thin-film transistor (M5) wherein a fourth clock (CKD) that changes from an OFF level to an ON level when a scanning signal outputted by the previous stage is to change from an OFF level to an ON level is supplied to the gate terminal, the drain terminal is connected to an output-control node (NA), and the scanning signal outputted by the previous stage is supplied to the source terminal; and a thin-film transistor (M6) wherein a third clock (CKC) that changes from an OFF level to an ON level when a scanning signal outputted by the next stage is to change from an OFF level to an ON level is supplied to the gate terminal, the drain terminal is connected to the aforementioned output-control node (NA), and the scanning signal outputted by the next stage is supplied to the source terminal.

A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.

An analo electronic watch is comprised of a display unit (2) for displaying a time by its hands, a step motor (3) for driving the hands, a motor driving unit (4) for controlling and driving the step motor at a prescribed hand driving interval in an ordinary case, a hand position detecting means for detecting positions of the hands, a hand position detecting means control unit (6) for intermittently controlling and driving the hand position detecting means (5) at a first detecting period, which is longer than the hand driving period, and a detecting period changing unit (7) for instructing thehand position detecting means (5) of changing the detecting period. When the detecting period changing unit (7) detects a detecting period changing condition, while the hand driving period for the step motor (3) is maintained, the detecting period changing unit (7) changes the hand position detecting period of the hand position detecting means (5) from the first detecting period to a second detecting period.

The invention relates to the technical field of parking management, and discloses a public parking space management system, including a background server, a mobile device, and ground locks arranged on public parking spaces, and each ground lock is equipped with a vehicle detection device and a ground lock controller , a battery, and a management method, including a vehicle detection device to detect whether a vehicle is parked, and the ground lock controller starts billing after receiving the signal of the vehicle parked, and controls the upper rotation of the baffle to withstand the vehicle chassis; at the same time, the background server calculates The unlock password synchronized with the ground lock controller; after the payment is successful, the ground lock controller controls the baffle to rotate down through the rotating device, and the car can be picked up and left. The invention manages automatically, charges according to time, can increase the profit of the manager, and integrates resources, and only needs to install a ground lock on the public parking space to complete the transformation, which is simple and convenient.

Disclosed is a data driver including a zero compensation resistor connected in series with a phase compensation capacitor between an output node of an input differential amplification stage and an output node of a succeeding amplification stage, and a control circuit that controls to switch a resistance value of the zero compensation resistor. The control circuit switches the resistance value of the zero compensation resistor to a first resistance value or a second resistance value larger than the first resistance value in response to turning off or on of an output switch that controls connection between the output terminal of an amplifying circuit and a data line.

In a temperature control device which maintains an obj ect to be controlled at a preset constant temperature and an arrayed waveguide grating optical wavelength multiplexer / demultiplexer, the adverse effect of the junction temperature of the semiconductor control element is eliminated for the purpose of simplifying the overall structure and improving operation efficiency sufficiently without any trouble. The object 10 to be controlled, which is an arrayed waveguide grating optical wavelength multiplexing / demultiplexing element, is fixed on the soaking plate 2 which is made from a good heat conductive material. The semiconductor control element 3 with a control terminal which functions as a heat generator by using its junction temperature and a temperature sensor 5 are fixed on the soaking plate 2. A negative feedback control is applied to the conduction condition of the semiconductor control element 3 in accordance with the error signal s3 which indicates the difference between the present temperature signal s2 obtained from the temperature detection signal s4 transmitted from the temperature sensor 5 and the preset target temperature signal s1. Consequently, the junction temperature of the semiconductor control element 3 is effectively used as a heating source not as a loss, thereby reducing the power consumption and stabilizing the performance.