41results about "Catalyst application resist" patented technology

A production process of a perforated porous resin base, comprising Step 1 of impregnating the porous structure of a porous resin base with a liquid or solution; Step 2 of forming a solid substance from the liquid or solution impregnated; Step 3 of forming a plurality of perforations extending through from the first surface of the porous resin base having the solid substance within the porous structure to the second surface in the porous resin base; and Step 4 of melting or dissolving the solid substance to remove it from the interior of the porous structure, and a production process of a porous resin base with the inner wall surfaces of the perforations made conductive, comprising the step of selectively applying a catalyst only to the inner wall surfaces of the perforations to apply a conductive metal to the inner wall surfaces.

A circuit board includes an electric circuit having a wiring section and a pad section in the surface of an insulating base substrate. The electric circuit is configured such that a conductor is embedded in a circuit recess formed in the surface of the insulating base substrate, and the surface roughness of the conductor is different in the wiring section and the pad section of the electric circuit. In this case, it is preferable that the surface roughness of the conductor in the pad section is greater than the surface roughness of the conductor in the wiring section.

A mechanism is disclosed for providing horizontally split vias in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first / second ones and third / fourth ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first / second conductive vias are plated onto the first through-hole and before third / fourth conductive vias are plated onto the second through-hole. The depth of these PTH plugs is controlled (e.g., using a photomask and / or variable laser power) to prevent the conductive vias from extending substantially beyond their respective internal conductive traces, thereby horizontally spitting the two conductive vias plated onto each of the through-holes. This advantageously increases wiring density up to 2×.

An object of the present invention is to provide a method for manufacturing a porous material in which complicated and fine through portions, recessed portions, and the like have been patterned. It is to provide a patterned porous molded product or nonwoven fabric, in which a plated layer has been selectively formed on the surfaces of the through portions and the recessed portions. With the invention, a mask having through portions in a pattern is placed on at least one side of the porous molded product or the nonwoven fabric. A fluid or a fluid containing abrasive grains is sprayed from above the mask, thereby to form through portions or recessed portions, or both of them, to which the opening shape of each through portion of the mask has been transferred, in the porous molded product orthe nonwoven fabric. The invention provides a porous molded product or a nonwoven fabric in which a plated layer has been selectively formed on the surfaces of the through portions or the recessed portions, or both of these, an electric circuit component, or the like.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board (10) comprises the following steps: drilling a hole on a substrate (11), the hole comprising a blind hole and / or a through hole (S1); on a surface (12) of the substrate, forming a photoresist layer having a circuit negative image (S2); forming a conductive seed layer on the surface (12) of the substrate and a hole wall (19) of the hole (S3); removing the photoresist layer, and forming a circuit pattern on the surface (12) of the substrate (S4), wherein Step S3 comprises implanting a conductive material below the surface (12) of the substrate and below the hole wall (19) of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

This invention provides a transparent electrically conductive film, which, while maintaining the light transparency of a transparent film, has excellent electrical conductivity, can be utilized for electromagnetic wave shielding, and does not cause inclusion of air bubbles in the lamination onto other base material, and a process for producing the same. The production process comprises the steps of forming a large number of concaves and convexes having an average height of not more than 0.1 μm on both sides or one side of a transparent film, forming a resist layer having a pattern shape opposite to the electrically conductive part in the electrically conductive film on the transparent film on its concave-convex side, applying a catalyst for plating onto the resist layer-formed face, separating the resist layer, forming a metal layer by plating, and blackening the metal layer, the metal layer satisfying 1≦W / T≦500 wherein W represents the width of the metal layer and T represents the height of the metal layer.

A method of manufacturing an interconnect substrate having a linear interconnect by electroless plating without using a plating resist, the method including: (a) forming a plurality of rows of linear catalyst layers on a substrate; and (b) depositing a metal on the linear catalyst layers by electroless plating to form a plurality of rows of linear metal layers, at least one of the rows of linear catalyst layers having a line width of 2 micrometers or less, and a total line width of the linear catalyst layers on the substrate being 10 micrometers or more.