91 results about "Metal oxide silicon" patented technology

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

A semiconductor device includes a silicon-controlled rectifier to protect an internal circuit from electrostatic discharge damage and a first metal-oxide-silicon field-effect transistor to apply a trigger voltage to the silicon-controlled rectifier. The first metal-oxide-silicon field-effect transistor including a gate electrode and a substrate which are electrically connected to each other.

The present invention includes methods and apparatus as described in the claims. Briefly, semiconductor diodes having a low forward conduction voltage drop, a low reverse leakage current, a high voltage capability and avalanche energy capability, suitable for use in integrated circuits as well as for discrete devices are disclosed. The semiconductor diodes are diode configured vertical cylindrical metal oxide semiconductor field effect devices having one diode terminal as the common connection between the gates and drains of the vertical cylindrical metal oxide semiconductor field effect devices, and one diode terminal as the common connection with the sources of the vertical cylindrical metal oxide semiconductor field effect devices. The method of manufacturing the vertical cylindrical metal oxide semiconductor field effect devices is disclosed. Various device terminations can be employed to complete the diode devices. Various embodiments are disclosed.

A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt.

A molecular detection chip including a metal oxide silicon-field effect transistor (MOSFET) on sidewalls of a micro-fluid channel and a molecular detection device including the molecular detection chip are provided. A molecular detection method, particularly, qualification methods for the immobilization of molecular probes and the binding of a target sample to the molecular probes, using the molecular detection device, and a nucleic acid mutation assay device and method are also provided. The formation of the MOSFET on the sidewalls of the micro-fluid channel makes easier to highly integrate a molecular detection chip. In addition, immobilization of probes directly on the surface of a gate electrode ensures the molecular detection chip to check for the immobilization of probes and coupling of a target molecule to the probes in situ.

A capacitance circuit assembly mounted on a semiconductor chip, and methods for forming the same, are provided. A plurality of divergent capacitors is provided in a parallel circuit connection between first and second ports, the plurality providing at least one Metal Oxide Silicon Capacitor and at least one Vertical Native Capacitor or Metal-Insulator-Metal Capacitor. An assembly has a vertical orientation, a Metal Oxide Silicon capacitor located at the bottom and defining a footprint, with a middle Vertical Native Capacitor having a plurality of horizontal metal layers, including a plurality of parallel positive plates alternating with a plurality of parallel negative plates. In another aspect, vertically asymmetric orientations provide a reduced total parasitic capacitance.

An apparatus and method for high-voltage transient blocking employing a transient blocking unit (TBU) that has at least one depletion mode n-channel device interconnected with at least one depletion mode p-channel device such that a transient alters a bias voltage Vp of the p-channel device and a bias voltage Vn of the n-channel device in concert. Specifically, the bias voltages are altered such that the p-channel device and n-channel device mutually switch off to block the transient. The depletion mode n-channel device employs a set of cascaded low-voltage depletion mode field effect transistors (FETs) such as metal-oxide-silicon field effect transistors (MOSFETs) connected source-to-drain to achieve the desired high-voltage operation of the TBU.

An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NFET or PFET is directly connected to the source of the second NFET or PFET, and wherein the gate of the second NFET or PFET is at a voltage value which is equal to or lower than the drain voltage value of the second NFET or PFET in the case of an NFET and equal to or higher than the drain voltage value of the second NFET or PFET in the case of a PFET.

A gate driving circuit for driving a power semiconductor element can include a MSINK that is an n-channel metal-oxide silicon field-effect transistor (MOSFET) with a low resistance value for rapidly drawing out the charges accumulated on the gate of an insulated gate bipolar transistor (IGBT), and a MSOFT that is an n-channel MOSFET with a high resistance value for slowly drawing out the charges. By shifting the time for turning ON of these MOSFETs, soft interruption can be performed rapidly and surely when overcurrent or short circuit current flows in the IGBT. Therefore, device breakdown is minimized or avoided and noise generation is suppressed.

A semiconductor device includes a silicon-controlled rectifier to protect an internal circuit from electrostatic discharge damage and a first metal-oxide-silicon field-effect transistor to apply a trigger voltage to the silicon-controlled rectifier. The first metal-oxide-silicon field-effect transistor including a gate electrode and a substrate which are electrically connected to each other.

A semiconductor switching device or amplifier combined in parallel with one or more active devices defined as starter devices. A starter device is used to reduce the terminal voltage of a switching device or amplifier to a dc level below about 0.4 volts which will then allow the switching device to easily change between the on or conducting state and the off or non-conducting state. Three different starter devices are utilized. The first being a Bipolar Junction Transistor (BJT), the second a Metal Oxide Silicon Field Effect Transistor (MOSFET), and the third consisting of three normally off JFETs connected serially. Generally, a single starter device is coupled across the terminals of a semiconductor switching device or amplifier, but it is possible and sometimes advantageous to couple two or more starter devices in parallel. In a first case, a symmetrical, normally off or enhancement mode JFET is used as the switch or amplifier. A starter device coupled between source and drain of the JFET will allow operation at dc voltage levels above 0.4 volts. In a second case, an asymmetrical, normally off JFET is used as the switch or amplifier. A starter device coupled between source and drain of the JFET will allow operation at dc voltage levels above 0.4 volts. In a third case, a normally off MESFET is used as the switch or amplifier. A starter device coupled between source and drain of the MESFET will allow operation at dc voltage levels above 0.4 volts.

A semiconductor apparatus includes a MOS transistor having a semiconductor substrate providing as a channel region between a source and a drain. A gate electrode is formed on the semiconductor substrate via a gate oxide film. A threshold voltage of the source side region of the MOS transistor is higher than that of the drain side region in a longitudinal direction of the channel region so that a saturation drain current can be constant and a λ performance can be improved while suppressing channel width and length.