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72 results about "Memory code" patented technology

Memory code integrity verification method and device

The embodiment of the invention discloses a memory code integrity verification method and device. The method comprises the following steps: sending at least two preset verification codes to a client, so that the client can select a target verification code from the verification codes to verify a designated memory code of the client; acquiring a client verification result returned by the client, wherein the client verification result comprises a returned value and an unique identifier of the target verification code; according to the unique identifier of the target verification code, carrying out matching between the client verification result and a target verification result corresponding to a server; and if the client verification result is identical to the target verification result, determining that integrity verification for the memory code of the client is successful. The method and device provided by the invention has the advantages that a threshold for memory code modification by HACK can be greatly raised, so that the integrity verification accuracy rate for the memory code of the client can be guaranteed, and the safety can be improved.
Owner:WUHAN DOUYU NETWORK TECH CO LTD

Structured memory graph network model for multiple rounds of spoken language understanding

The invention discloses a structured memory graph network model for multiple rounds of spoken language understanding, which is composed of an input coding layer, a memory coding layer, a feature aggregation layer and an output classification layer, dialogue behaviors generated by spoken language understanding tasks are used to replace texts as memory nodes for coding, and the dialogue behaviors are formatted representations containing semantic framework information. And the unstructured characters are converted into a structured triple. A graph attention network is used for replacing a recurrent neural network and an attention mechanism to achieve feature aggregation, sequence information between the attention mechanism and dialogue nodes is reserved, and model learning how to effectivelyutilize structured memory nodes is facilitated. According to the network model, the encoding dialogue behavior replaces a historical dialogue text to serve as a memory unit, original information of asemantic framework is reserved to the maximum extent, and the problems that in the prior art, noise is generated in complex occasions due to the fact that text information depends on a model, and operation efficiency is low are solved.
Owner:NORTHWEST NORMAL UNIVERSITY

Program mechanical code compiling method for programmable logic controller

The invention relates to a program machine code compilation method of a programmable logic controller (PLC). After reading a PLC program, mnemonics codes in the program are searched. Provided that all the syntaxes of the mnemonics codes in the PLC program are logical, the PLC program is converted into a C Language file. And then the C language file is converted into a C Language target file which is linked with a library file. If the link is successful, a link file is converted into a machine code for being directly operated by the PLC so as to control external input and output connection points (EXIO) on a human-computer interface.
Owner:DELTA ELECTRONICS INC

Fast memory coding method and device based on multi-synaptic plasticity spiking neural network

The invention provides a fast memory coding method based on a multi-synaptic plasticity pulse neural network. The fast memory coding method comprises the steps of 1, converting external stimulation into an input pulse sequence based on a hierarchical coding strategy; 2, after the pulse neural network receives an input pulse, updating a membrane potential of neurons of an output layer based on an improved SRM model; 3, updating a synaptic weight input to an output layer by using a supervisory group Tempotron, and activating neuron memory input of the output layer; step 4, after the neurons of the output layer are activated, using the unsupervised STDP to update synaptic weights among the activated neurons in the layer, and forming an enhanced cyclic sub-network storage memory; and step 5, while executing the step 4, using unsupervised inhibition synaptic plasticity, updating a synaptic weight between an inhibition layer and an output layer, and inhibiting separation of distribution time of neural populations with different inputs of feedback guarantee memories. The invention further provides a fast memory coding device based on the multi-synaptic plastic spiking neural network. According to the invention, the coding speed and stability of memory are effectively improved.
Owner:ZHEJIANG LAB +1

SRAM memory cell and circuit for improving read/write stability of SRAM memory cell

The invention relates to the technical field of electronic communication, in particular to an SRAM memory cell and a circuit for improving the read/write stability of the SRAM memory cell. The SRAM memory cell comprises a first switch device, a second switch device, a first inverse unit and a second inverse unit, wherein the first switch device is controllably connected with a first bit line to a first memory code; the second switch device is controllably connected with a second bit line to a second memory code; the first inverse unit is connected between the first switch device and the second switch device in series; the first inverse unit is provided with a first input end and a first output end; the first memory code is defined at the first output end; the second inverse unit is connected between the first switch device and the second switch device in series; a second input end of the second inverse unit is connected with the first output end; a second output end of the second inverse unit is connected with the first input end; and the second memory code is defined at the second output end. According to the SRAM memory cell and the circuit, better read/write ability is provided, the reliability of the SRAM memory cell is improved without adding overmuch extra circuits, the complexity of circuit design is reduced and the area is saved.
Owner:SPREADTRUM COMM (SHANGHAI) CO LTD

Method for examining memory code of printed circuit board

The invention discloses a method for examining a memory code of a printed circuit board, which comprises the following steps: adding a checking code at data end of the code, after writeing in a memory, calculating a checksum of the data of a main code part by a timing controller, comparing the calculated checksum and the checking code, outputting a test pin to a probe for displaying the comparison result to reach the purpose of examining whether the write-in code is correct or not. The method of the invention is capable of enhancing the work efficiency of the write-in code examination in the memory.
Owner:SHENZHEN CHINA STAR OPTOELECTRONICS TECH CO LTD

Multiple anti-forge ink with memory code and testing method thereof

The invention is a multiple anti-falsification ink with a memory code and a method of detecting the ink marks of writing with it, synthesized of general ink, magnetic memory material, infrared fluorescent material and UV fluorescent material, etc. and the detecting method: making magnetic-electric conversion on the code information in the magnetic material in the ink marks and detecting, identifying the code information, and the infrared light generator excites infrared fluorescent information in the ink marks and the UV light of the UV lamp excites long-short wavelength UV fluorescent information in the ink marks. It has good anti-falsification effect, and the handwriting contains an electromagnetic code, infrared fluorescent information and UV fluorescent information, detected by special apparatuses and the code has uniqueness, so that the falsifier is difficult to simulate, thus able to effectively the occurrence of forging signatures, altering, forging written pledges, and other illegal activities. It is applied to important bills of documents and notes, signature, contracts and documents, etc.
Owner:熊春宁

GNSS receiver and method for GNSS memory code generation

The invention provides a Global Navigation Satellite System (GNSS) receiver. In one embodiment, the GNSS receiver comprises a memory, a buffer, a correlator, and a selector. The memory stores a memory code and outputs a portion of the memory code as a first code segment. The buffer comprises a plurality of component buffers and stores the first code segment into one of the component buffers in order. The selector selects a portion of the first code segments stored in the buffer as a second code segment output to the correlator according to the code phase selection signal, wherein the data length of the second code segment is equal to a correlation data length of the correlator. The correlator calculates a correlation between a received GNSS signal with the correlation data length and the second code segment.
Owner:MEDIATEK INC

Method of transforming original address date for reducing address memory space with the code

This invention relates to one method to reduce address memory space by use of code type to convert original address applied in digital move device, which comprises the following steps: firstly, establishing compression codes list; then user inputting any detail complete address data; through compression code comparison list converting the original address data into compression codes address data; finally, converting the memory codes form address data to reduce address memory space.
Owner:HUANDA COMPUTER (SHANGHAI) CO LTD +1
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