159 results about "Memory failure" patented technology

The present invention is a system and method for recovering from memory failures in computer systems. The method of the present invention includes the steps of: identifying a predetermined instruction sequence; monitoring for memory access errors in response to the request; logging a memory access error in an error logging register; polling the register for any logged memory access error during execution of the instruction sequence; and raising exceptions, if the memory access error is logged. Within the system of the present invention, memory access errors are stored in an error logging register, machine check abort handles are masked, and memory controllers are under full control of the software so that memory access errors can be intercepted and responded to without necessitating a system reboot or application restart. The present invention is particularly applicable to O/S code which can not otherwise recover from memory errors except by rebooting.

The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources. The present invention further provides a redundant resource allocation system, which uses a bad location list and an associated bad location list to classify failed memory locations according to a predetermined priority sequence, and allocates redundant resources to repair the failed memory locations according to the priority sequence.

An ECC based system and method within an integrated circuit memory for self-repair of a failed memory element is disclosed. The method includes processing, within the integrated circuit, data and check bits retrieved from addressed memory locations therein. The locations of memory failures are automatically recorded within the integrated circuit. Logic circuits within the integrated circuit automatically identify failure patterns based on the locations. Based on the identified failure patterns, logic circuits within the integrated circuit then permanently replace a failed memory element with an appropriate redundancy element, using devices such as electronic fuse or antifuse. In this manner, the integrated circuit automatically identifies and effects self repair of a failed memory element therein.

A system and method for memory failure recovery is disclosed. The method discloses the steps of maintaining a predetermined number of duplicate and primary processes; keeping the processes in synchronization; managing the processes so that a single process image is presented to an external environment; detecting a computer system exception which affects one of the processes; and terminating the affected process. The system discloses, a primary process memory space which hosts a primary process; a duplicate process memory space which hosts a duplicate process corresponding to the primary process; a synchronization buffer which keeps the duplicate process in synchronization with the primary process; a processor which generates an exception signal in response to detection of a memory failure condition which affects the primary process; and an operating system which receives the exception signal, terminates the affected primary process, and maintains a predetermined number of primary and duplicate processes.

A reliable fault-tolerant I/O controller supporting redundant synchronous memories is described. The I/O controller includes multiple I/O control logic units where each I/O control logic unit is in communication with a host server and external peripheral devices. Each I/O control logic unit includes a processor, a memory, and a memory controller. A master I/O control logic unit services I/O transactions from the host server and the external peripheral devices. A slave I/O control logic unit operates in a quiescent state until the master I/O control logic unit experiences a memory failure. At such time, the slave I/O control logic unit resumes operation of the I/O controller. In order to facilitate the switchover from the master I/O control logic unit to the slave I/O control logic unit, the master memory controller performs concurrent memory write operations in both the master and slave memories. The concurrent memory write operations ensure that the memories in both I/O control logic units are in a consistent state in order for the switchover to occur without loss of data.

Upon occurrence of a memory error which is difficult to correct, CPU interrupts a process under execution in response to interrupt signal output from error detection device, and transfers the control to the OS. The OS references attributes of a page stored in a page frame which has suffered the memory error. When read-only is indicated, physical memory management table is updated to set the page frame, which has suffered the error, into a disabled state. Then, page table is updated such that a virtual page stored in the page frame which has suffered the error is not assigned to any page frame, followed by resumption of the execution of the process. After execution of the process is resumed, a page fault process is invoked to store the virtual page which has encountered the memory error in another normal page frame.

Memory reliability is improved by using redundancy to repair errors detected by ECC. In one embodiment, redundancy repairs errors which cannot be corrected by ECC. The redundancy can employ the use of electronic fuses, enabling repairs after an IC containing the memory is packaged. Redundancy can also be performed prior to packaging of the IC.

The invention relates to the field of software performance test, and particularly relates to a software accelerating life test method used for carrying out life test to the software producing aging phenomena by adopting the accelerating life test theory. The software accelerating life test method comprises the following steps: adding codes injected with memory failures; setting accelerating-level pressure value N as 4, 8, 12 and 16, and running a program; recoding failure time TTF, and saving data; estimating sample distribution of software lifetime; establishing a suitable relationship between the lifetime and the pressure, and estimating distribution of average failure time of system being tested under a non-accelerating circumstance. The deployment and implementation of the invention aims to carry out an accelerating life test to the software producing aging phenomena, the lifetime data of software under an accelerating circumstance is obtained through the short time-consuming accelerating life test, the real lifetime of the software under the non-accelerating circumstance is calculated, so that the probability distribution of the software lifetime under a normal use condition is obtained.

An embodiment of the invention provides a memory migration method, a memory migration device and equipment. The method includes the steps: detecting whether at least one first memory segment is in an abnormal state or not; generating a memory migration instruction when at least one first memory segment is in the abnormal state; analyzing the memory migration instruction; acquiring memory information parameters for indicating whether at least one first memory segment corresponds to at least one progress or not in the memory migration instruction; and migrating relevant data corresponding to at least one process to at least one second memory segment in the normal state from at least one first memory segment and storing the relevant data when at least one first memory segment corresponds to at least one process. Therefore, the problem of service interruption in a memory caused by memory failure in the prior art can be solved, so that running stability and reliability of service processes in a system are improved.

The invention provides a fault processing method for a memory CE. The fault processing method comprises the steps of enabling a BIOS to judge whether Patrol Scrub UCE occurs or not by reading a presetregister; if not, judging whether the common CE count meets a missed error threshold value or not; and if the Patrol Scrub UC or the common CE count meets the missed error threshold value, triggeringSMI interruption. According to the invention, when the Patrol Scrub UCE occurs, SMI interruption is triggered the BIOS is prevented from counting as a common CE, so that the BIOS can discover the Patrol Scrub UCE in time; server operation and maintenance personnel can obtain memory fault information in time; and monitoring of the memory state of the server is facilitated. The invention further provides a fault processing system for the memory CE, a computer readable storage medium and fault processing equipment for the memory CE, which have the above beneficial effects.

A semiconductor device for testing memory, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, and a fail detector for determining memory failure. Another semiconductor device for testing at least one of a plurality of memory devices, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, a reference data generator for generating reference data, and a fail detector for determining memory failure. A method of determining memory failure, including writing data to a plurality of memory devices, reading the data from the plurality of memory devices, comparing corresponding addresses of the read data simultaneously, outputting a single fail signal when the comparing step determines at least one of the read data from the plurality of memory devices as not being equal. A semiconductor device for testing memory, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, a reference data generator for generating reference data, a selection circuit for selecting the read data from one of the plurality of memory devices, and a comparator for comparing the read data from one of the plurality of memory devices with the reference data. A semiconductor device for testing memory, including a BIST controller for testing a plurality of memory devices, an address and control signal generator for generating address and control signals for reading data from the plurality of memory devices, a test data generator for generating test data, and a single comparison unit for determining memory failure in at least two of the plurality of memory devices. A method of determining memory failure, including writing data to a plurality of memory devices, reading the data from the plurality of memory devices, comparing corresponding addresses of the read data of at least two of the plurality of memory devices in a single comparison unit.

The invention provides a method and a device for handling faults. The method includes acquiring information of available memory capacity of storage nodes and the quantities of object storage devices OSD; rejecting OSD addition operation on target storage nodes when ratios of the available memory capacity of the target storage nodes to the quantities of the OSD are smaller than first preset thresholds and setting partial OSD of the target storage nodes in first types of non-working Down states to allow the ratios of the available memory capacity of the target storage nodes to the quantities ofthe other OSD to be larger than or equal to the first preset thresholds. The other OSD refer to the available OSD, except for the partial OSD set in the first types of Down states, among the OSD of the target storage nodes. The method and the device have the advantage that risks of possible OSD performance bottleneck and data recovery failure after faults of memories on the storage nodes occur canbe prevented by the aid of the method and the device.

A circuit architecture of a memory device includes: a main memory circuit for implementing storage of user data; and the main memory fault repair circuit is used for realizing repair of storage faultsin the main memory. The main memory circuit comprises a memory array circuit designed in an array partitioning mode. In a main memory failure repair circuit, a CAM is used to store a failure addressof a main memory, and an ROM is used to store configuration data for configuring a programmable address decoder in a main memory circuit. A memory fault repair method includes repair schemes for wordfaults, row faults, and column faults of a memory device. A memory fault test and fault repair process for fault detection, fault analysis, and fault repair prior to memory device packaging includes arepairability determination method of a memory device and an operating method of programming a fault repair circuit of the memory device.

The invention provides a method for automatically positioning an internal memory fault. The method includes the following steps: reading a value of a machine check architecture (MCA) register, analyzing the value to obtain physical address of a fault internal memory, obtaining staggering state of the internal memory between a socket, obtaining the socket value of the fault internal memory according to the staggering state, acquiring channel value and excursion in the channel according to the staggering state of the internal memory physical address and the internal memory between the socket, acquiring groove position information of the fault internal memory according to the excursion in the channel and positioning the fault internal memory according to the socket value, the channel value and the groove position information of the fault internal memory. The method can accurately position groove position of the fault internal memory, maintains the internal memory matched with other methods, improves internal memory fault monitoring rate and reduces data center operation and maintenance cost. A device for automatically positioning the internal memory fault is further provided.

The invention discloses a word line resistance test method and a three-dimensional memory failure analysis method. According to the word line resistance test method, first, multiple through hole connecting lines in a first step region and a second step region of a three-dimensional memory are exposed; second, by forming a connection metal layer in the first step region, multiple word lines are connected with the connection metal layer through the through hole connecting lines; and last, resistance of every two to-be-tested connecting lines is tested in the second step region, the resistance of the three to-be-tested connecting lines is calculated according to first test resistance, second test resistance and third test resistance obtained through testing, that is, word line resistance corresponding to the three to-be-tested connecting lines is obtained, therefore, measurement of the word line resistance in the three-dimensional memory is realized, and a foundation is laid for performing failure analysis on the three-dimensional memory.

A 3D NAND memory and a method for forming the same are disclosed. The forming method includes providing a semiconductor substrate on which a stacked structure is formed, wherein the stacked structureincludes a plurality of sacrificial layers and isolation layers which are alternately stacked, the stacked structure has a first channel hole and a second channel hole in communication with the firstchannel hole, the second channel hole has an alignment offset with respect to the first channel hole, and a step is formed at a boundary between the first channel hole and the second channel hole; forming a charge storage layer on the sidewalls and the bottoms of the first channel hole and the second channel hole; forming a channel hole sacrificial layer on the charge storage layer; forming a protective layer on the channel hole sacrificial layer; successively etching the protective layer, the channel hole sacrificial layer, and the charge storage layer on the bottom of the first channel holeto form an opening exposing the surface of the semiconductor epitaxial layer. The method of the present invention prevents the charge storage layer at the step from being broken or damaged, thereby preventing memory failure.