Universally accessible fully programmable memory built-in self-test (mbist) system and method

Abstract

A universally accessible fully programmable memory built-in self-test (MBIST) system including an MBIST controller having an address generator configured to generate addresses for a memory under test, a sequencer circuit configured to deliver test data to selected addresses of the memory under test and reading out that test data, a comparator circuit configured to compare the test data read out of the memory under test to the test data delivered to the memory under test to identify a memory failure, and an externally accessible user programmable pattern register for providing a pattern of test data to the memory under test. The system includes an external pattern programming device configured to supply the pattern of test data to the user programmable data pattern register.

Description

[0001] Cross References to Related Applications [0002] This application claims priority based on US Provisional Patent Application No. 60 / 471,408, filed May 16, 2003, the contents of which are incorporated herein by reference. technical field [0003] In general, the present invention relates to memory built-in self-test (MBIST) for testing memories, and more particularly to improved systems and methods for implementing universally accessible and fully programmable MBIST. Background technique [0004] Complex system-on-chip (SoC) designs, such as ASIC chips, typically contain large amounts of embedded memory. The embedded memory can be static random access memory (SRAM), dynamic random access memory (DRAM), cache, register file and even FLASH memory. The embedded memory of the SoC chip is internal, so it is not easy to access from the outside for testing. As a result, MBIST systems on SoCs are a common method for testing embedded memory arrays on SoCs. [0005] Typicall...

AI Technical Summary

Problems solved by technology

While the 6,452,848 patent appears to disclose a programmable memory test pattern generator, the design is limited to test data patterns that can be generated by extending hardwired XOR logic gates

The design also cannot accept external programming (such as external to the MBIST controller) to generate test data patterns

In addition, extended hardwired logic gates, address scramble registers, and data word registers must also be incremented and / or decremented

Therefore, the MBIST design of the 6,452,848 patent cannot run at the same speed as the memory under test due to the delay caused by expanding the logic gates and the delay associated with incrementing or decrementing the address and data word registers (requiring at least one clock cycle)

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