505results about How to "Reduced pin count" patented technology

A bussed haptic actuator system includes a plurality of haptic actuators and a master control subsystem. Each haptic actuator includes a memory with an address storable therein and a slave controller subsystem configured to control the actuator in response to a received command signal. The master control subsystem is connected via a bus to the plurality of haptic actuators. The master control subsystem includes sequencer configured to determine which of the plurality of haptic actuators are to be activated and logic configured to provide, on the bus, a command signal including one or more addresses corresponding to haptic actuators to be activated as determined by the sequencer.

One embodiment of the present invention provides a system that uses encoded memory control signals to reduce pin count on chips that generate and drive memory control signals. During operation, the system receives encoded memory control signals from a memory controller, wherein the memory control signals were encoded to reduce the number of memory control signals, and wherein the encoded memory control signals are received at a buffer chip, which is external to the memory controller. Next, the system decodes the encoded memory control signals on the buffer chip to restore the memory control signals, and then drives the memory control signals from the buffer chip to corresponding memory modules in the system memory. By transferring the memory control signals in encoded form from the memory controller to the buffer chip, fewer pins are required on both the memory controller chip and the buffer chip.

The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources. The present invention further provides a redundant resource allocation system, which uses a bad location list and an associated bad location list to classify failed memory locations according to a predetermined priority sequence, and allocates redundant resources to repair the failed memory locations according to the priority sequence.

The invention provides a touch control structure which is characterized in that the touch control structure comprises multiple rows of driving electrodes, multiple rows of induction electrodes, multiple rows of drive signal pins and multiple induction signal pins, wherein each row of the driving electrodes comprises multiple driving electrodes, each row of the induction electrodes comprises multiple induction electrodes, the induction electrodes in each row of the induction electrodes are divided into multiple groups, and the multiple rows of the induction electrodes and the multiple rows of the driving electrodes are arranged at intervals; the driving electrodes in each row of the driving electrodes are correspondingly and electrically connected with driving signal ends one to one; the induction electrodes in one group are electrically connected with the different induction signal pins, one induction electrode in every group is electrically connected with the same induction signal pin, and one driving electrode corresponds to one group of induction electrodes.

A bus system (BS) for selectively controlling a plurality of identical slave circuits (slave A) comprises a bus (B) having a clock line (CLOCK) and at least one data line (DATA). The bus system (BS) includes at least one master circuit (1) and a plurality of slave circuits (2) with a group of identical slave circuits (slave A) connected to said bus (B). Each of the identical slave circuits (slave A) comprises an input-terminal (AD). The bus system (BS) further includes a selection circuit (3) connected to said bus (B), said selection circuit (3) is connected to each of said input-terminals (AD) for configuring at least one of the identical slave circuits (slave A) to be addressable by a master circuit (1) via said at least one data line (DATA).

An apparatus, system, and method for controlling data transfer between a serial data link interface and memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple serial data links and multiple memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

The invention applies to the field of liquid-crystal lenses, and provides a liquid-crystal zoom lens and an electronic device. By connecting conductive media between every two adjacent annular waveband electrodes of transparent electrodes of a substrate and extracting the electrodes through gap channels of the annular waveband electrodes, the invention greatly reduces the number of pins required by a step electric field, is simple in control, reduces the interference in the step electric field, and reduces space area occupied by the substrate.

The invention discloses a testing method which comprises the following steps: acquiring the testing procedure from automatic test equipment (ATE) by using a device under test (DUT) and initializing according to the testing procedure; receiving test signals by using the DUT, and testing according the test signals, and outputting test results; and reading the test results by using the ATE and determining whether the DUT conforms to the requirements according to the test results. The invention simultaneously discloses a testing system. By applying the method and the system, the test cost can be reduced, the fault coverage can be improved, and the invention can be implemented easily.

An active display device comprises a sub-pixel array and a sub-pixel array driving circuit; all of the sub-pixels of the same column in the sub-pixel array are connected with the same data line, each data line is connected with and located between two adjacent columns of sub-pixels, two columns of sub-pixels are arranged between two adjacent data lines; each line of sub-pixels correspond to two scanning lines, the sub-pixels of odd-numbered columns in the same line are connected to one of the scanning lines, the sub-pixels of even-numbered columns in the same line are connected to the other one of the scanning lines, and the sub-pixels connected with each data line are disposed in the same line. When driving, the sub-pixels of odd-numbered columns in the same line are controlled by one scanning line, and the sub-pixels of even-numbered columns in the same line are controlled by the other scanning line. The number of the scanning lines is decreased by half compared with the traditional organic display device, the column inversion and the point inversion of the polarity of the sub-pixel array can be realized, and thereby improving the process yield, reducing the cost and improving the display effect while realizing the high fining.

The invention discloses an optical module and an optical line terminal device. The optical module includes: a housing, a circuit board, an optical assembly and a storage unit. The optical assembly is in electrical connection to the circuit board and is intended for generating an optical signal based on an electrical signal; or is intended for converting the received optical signal to an electrical signal; the storage unit is in electrical connection to the circuit board, and is intended for storing the working parameters of the optical assembly; the circuit board, the optical assembly and the storage unit are packaged inside the housing, and the circuit board is provided with an electrical interface thereon, and the electrical interface have pins which are in one by one corresponding connection to a driving end of the optical assembly and a data transmission base pin of the storage unit. When the optical module works, the working parameters of the optical assembly are transmitted to an external master control chip through the electrical interface, and the external master control chip configures an external drive circuit on the basis of the working parameters of the optical assembly, and the external drive circuit drives the optical assembly through the electrical interface. The optical module only packages the optical assembly and the storage unit and is conductive to the reduction of the volume of the optical module.

A terminal device consists of power supply management module PMU and connector with a charge pin and two detection pins. It is featured as starting up charge mode of charger to receive current from charge pin for carrying out charge when voltage input on said charge pin is detected by PMU module and two said detection pins are short-circuit, starting up charge mode of universal serial bus USB to receive current from said charge pin for carrying out charge when voltage input on said charge pin is detected and two said detection pins are not short-circuited.

An optical communication module includes a physical-layer unit having a first control unit for receiving a write destination address and NVR data from a host via a serial bus, and for carrying out serial/parallel conversion of the received write destination address and NVR data, and storing them in registers of the first control unit, respectively, and a second control unit for copying the stored write destination address and NVR data to corresponding registers of the second control unit, respectively, and for carrying out parallel/serial conversion of the write destination address and NVR data which are copied to the registers of the second control unit, respectively, and sending them to either an EEPROM or a flash memory of a microcomputer, as well as a write command, via another serial bus to write the NVR data into either the EEPROM or the flash memory of the microcomputer.