742 results about "Single process" patented technology

A process device providing total fluid flow control is provided. The device includes a closure mechanism disposed in a flow conduit. The closure mechanism, which is preferably an iris-type diaphragm, provides a variable internal diameter. The device includes a differential pressure sensor for sensing the differential pressure on opposite sides of the diaphragm. A controller receives an indication of differential pressure and generates a control signal to an actuator that actuates the closure mechanism. The closure mechanism, differential pressure sensor and controller create a closed-loop flow controller in a single process device.

The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density "system on chip" architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.

Bone marrow aspiration devices and methods are disclosed for use in preparing a substrate. In general, the device includes an elongate penetrating element, a chamber adapted to retain a substrate, and a fluid extraction mechanism that is effective to pull fluid through the elongate penetrating element, into the chamber, and through the substrate. The device is particularly advantageous in that it will allow for the removal of fluids from a patient's body and the preparation of a substrate in a single process, thereby providing a more efficient method and device for preparing a substrate.

A global optimization framework for optical character recognition (OCR) of low-resolution photographed documents that combines a binarization-type process, segmentation, and recognition into a single process. The framework includes a machine learning approach trained on a large amount of data. A convolutional neural network can be employed to compute a classification function at multiple positions and take grey-level input which eliminates binarization. The framework utilizes preprocessing, layout analysis, character recognition, and word recognition to output high recognition rates. The framework also employs dynamic programming and language models to arrive at the desired output.

A semiconductor structure (and method for forming) having transistors having both metal gates and polysilicon gates on a single substrate in a single process is disclosed. The method forms a gate dielectric layer on the substrate and forms the metal seed layer on the gate oxide layer. The method patterns the metal seed layer to leave metal seed material in metal gate seed areas above the substrate. Next, the method patterns a polysilicon layer into polysilicon structures above the substrate. Some of the polysilicon structures comprise sacrificial polysilicon structures on the metal gate seed areas and the remaining ones of the polysilicon structures comprise the polysilicon gates. The patterning of the polysilicon gates forms the sacrificial gates above all the metal gate seed areas. Following that, the invention forms sidewall spacers, and source and drain regions adjacent the polysilicon structures. Then, the invention protects the polysilicon gates, removes the sacrificial polysilicon structures, and plates the metal gate seed areas to form the metal gates. The sidewall spacers self-align the metal gates. The plating process forms the metal gates of pure metal. All thermal processing that raises the temperature above a damage threshold for the metal is performed before the plating process.

A digital image system and method for combining bad pixel correction and demosaicing in a single process is provided by interpolating sensor values for pixels immediately spatially adjacent to the current pixel being examined to detect defective pixels, and using the interpolated values for demosaicing. If the sensor value of the current pixel being examined is outside of a range of sensor values determined from the interpolated values by more than a configurable threshold amount, the current pixel is considered defective, and replaced using an estimated value from the neighboring pixels. The interpolated values calculated for use in detecting bad pixels can further be used as the interpolated values for demosaicing purposes