The invention relates to an ECO (
Engineering Change Order) optimization method of a multiplier based on
standard cell library extension. The traditional optimization method is limited in finite drive capability of the standard cells in the
library, and cannot realize the shortest
path delay. The ECO optimization method comprises the steps as follows: firstly, generating a
layout of an extension unit, and characterizing the extension unit to obtain an extension unit
library, wherein the characterizing the extension unit comprises characterizing the
delay information, characterizing an input port
capacitor, characterizing the
power consumption, characterizing the area and characterizing a
performance function; secondly, performing
time series analysis on the multiplier to obtain a key path of the multiplier; and lastly, enabling the gate effects of all stages of the key path of the multiplier to be the same by using the extension unit library so as to obtain the shortest
path delay. According to the ECO optimization method, on the premise of not remarkably increasing the
design cycle, the key path of the multiplier is analyzed, the shortest
path delay is realized, and the performance of the multiplier is improved; in addition, the design
automation is conveniently implemented, and the ECO optimization method is also suitable for the rear-end ECO optimization of other digital systems.