A power FET (100) comprising a leadframe including a pad (110), a first lead (111), and a second lead (112); a first
metal clip (150) including a plate (150a), an extension (150b) and a
ridge (150c), the plate and extension spaced from the leadframe pad and the
ridge connected to the pad; a vertically assembled stack of FET chips in the space between the plate and the pad, the stack including a first n-channel FET
chip (120) having the drain terminal on one surface and the source
and gate terminals on the opposite surface, the drain terminal attached to the pad, the source terminal attached to a second clip (140) tied to the first lead; and a second n-channel FET
chip (130) having the source terminal on one surface and the drain
and gate terminals on the opposite surface, the source terminal attached to the second clip, its drain terminal attached to the first clip; wherein the drain-source on-resistance of the FET stack is smaller than the on-resistance of the first FET
chip and of the second FET chip.