40results about How to "Reduced risk of splintering" patented technology

An embodiment of the invention relates to the technical field of a semiconductor and especially relates to a wafer tapeout method so as to improve stress status of a wafer. The method comprises the following steps: carrying out front-side treatment process on the wafer to prepare scribing grooves in the front-side treatment process; after the front-side treatment process of the wafer, etching the scribing grooves; and carrying out back-side process on the wafer. The scribing grooves are etched after the front-side treatment process, so that the stress inside the wafer can be released, and the risk of wafer fragmenting and breaking in the follow-up process, such as back thinning, is reduced greatly.

The invention relates to an elastic buffering decorating plate in building plates. The elastic buffering decorating plate comprises a decorating plate body and an adhering plate body, and a groove cavity for allowing the adhering plate body to be slidably embedded into and being matched with the adhering plate body in a telescopic mode is formed in the reverse side of the decorating plate. At least one plate edge of the adhering plate body and the corresponding groove inner edge in the groove cavity of the decorating plate body are slidably limited through a limiting sliding block, and the plate edges of the adhering plate body are provided with limiting sliding grooves slidably matched with the limiting sliding blocks. The ends, close to the reverse side of the adhering plate body, of the limiting sliding grooves are provided with assembling groove bodies with the depths being larger than the depths of the limiting sliding grooves. When the limiting sliding blocks are located in the limiting sliding grooves, part of each limiting sliding block protrudes out of the corresponding plate edge of the adhering plate body. When the limiting sliding blocks are located in the assembling groove bodies, the limiting sliding blocks are not exposed relative to the plate edges of the adhering plate body correspondingly. The groove inner edges, corresponding to the plate edges, in a recessed cavity of the decorating plate body are provided with positioning grooves for positioning the limiting sliding blocks, and the parts, protruding out of the plate edges of the adhering plate body when the limiting sliding blocks are located in the limiting sliding grooves, of the limiting sliding blocks are positioned by the positioning grooves. The recessed cavity of the decorating plate body is internally provided with buffering springs abutting against the decorating plate body and the adhering plate body. The elastic buffering decorating plate has the advantages that buffering is achieved, and replacement is easy.

The invention relates to a lamination technology of a film photovoltaic assembly. The lamination technology comprises the flows of 1) preparing a battery chip; 2) leading a transmission structure; 3) laying a connection film layer; 4) laying a backboard package; 5) laminating a battery assembly; and 6) completing the battery assembly. In the flow 5), the lamination temperature is controlled between 160 and 165 DEG C, the lamination time is kept within 6-8 min, the vacuum-pumping time is controlled within 3 to 5 min, the laminating vacuum degree is kept between 0 and 50 Pa, and the laminating pressure is controlled between 0.4 and 0.6 that of the atmospheric pressure. The qualified rate and production efficiency of products are effectively improved, and the film photovoltaic assembly of higher reliability, longer service life and high stability and consistency can be obtained in the lamination process via optimization.

An embodiment of the invention relates to the technical field of a semiconductor and especially relates to a wafer tapeout method so as to improve stress status of a wafer. The method comprises the following steps: carrying out front-side treatment process on the wafer to prepare scribing grooves in the front-side treatment process; after the front-side treatment process of the wafer, etching the scribing grooves; and carrying out back-side process on the wafer. The scribing grooves are etched after the front-side treatment process, so that the stress inside the wafer can be released, and the risk of wafer fragmenting and breaking in the follow-up process, such as back thinning, is reduced greatly.

The invention provides a semiconductor structure with a low resistance substrate and low power loss. The semiconductor structure comprises a semiconductor unit, a first conductive structure, a first conductive material and a second conductive structure, wherein the semiconductor unit is provided with a substrate, and the substrate is positioned at one side of the semiconductor unit and is provided with at least one hole; the first conductive material is positioned in the hole in a filling-in or underfilling way, and the first conductive structure is positioned on one surface of the side of the semiconductor unit; and the second conductive structure is positioned on the surface of the other side of the semiconductor unit different from the semiconductor substrate. The semiconductor structure can effectively reduce the resistance of the substrate, and further reduce the power loss during the breakover on the semiconductor structure, and also has a longer service life. In addition, without adding additional equipment, the advantages of the current packaging factory capacity can be continuously utilized, so that the power loss and potential die crack risks are further reduced.

The invention discloses a modular multi-chip packaging structure and a packaging method thereof. A plurality of packaging units are arrayed on a substrate, and the packaging unit is formed by a plurality of chips stacked in steps. The lead ends of the chips stacked in steps are located on the steps. On the surface, the lead ends of multiple chips are connected by chip wiring, and the chips do not need to be wired, which reduces the packaging volume of the chip and avoids the loss of electrical performance on the wirebond line. The plastic package is plastic-sealed. The bottom of the first plastic package is provided with an etched circuit connected to the chip wiring, and the connecting wiring is arranged on the substrate. The etched circuit at the bottom of the first plastic package is connected to the connection wiring on the substrate. Multiple packaging units are sealed on the substrate, and the chips are vertically placed on the substrate after plastic packaging. The independent modules can be packaged together to integrate different functions, which breaks the limitations of traditional multi-chip packaging, and has a simple structure. The connection is stable.

The invention provides a droplet jetting device and a related method. The droplet jetting device comprises a piezoelectric chip and an interdigital transducer arranged on the upper surface of the piezoelectric chip, the ratio of the thickness of the piezoelectric chip to the period of the interdigital transducer is 1-3, the interdigital transducer is driven by a radio frequency signal to excite surface acoustic waves and bulk acoustic waves in the piezoelectric chip, and the surface acoustic waves and the bulk acoustic waves are reflected on the upper surface and the lower surface of the piezoelectric chip to generate composite acoustic waves so as to drive to-be-driven liquid on a liquid attachment area to stretch in the direction perpendicular to the surface of the piezoelectric chip to form a liquid column, so that the liquid column generates a liquid drop pinch-off effect at the end part, and a single liquid drop is ejected, the liquid attachment area is located on the upper surface and / or the lower surface of the piezoelectric chip and corresponds to the area covered by the surface acoustic wave generated by the interdigital transducer propagating along the surface of the piezoelectric chip. The problems that a device is complex in structure, high in cost, low in efficiency and inconvenient to achieve on-demand jetting are solved.

The present application discloses a method for holding an ultra-thin semiconductor wafer (1) in a semiconductor integration process. The main steps comprise: 1) spin-coating a first temporary bonding adhesive (3) on a front surface of a first temporary carrier (2); 2) bonding a front surface of an ultra-thin semiconductor wafer to the front surface of the first temporary carrier; 3) spin-coating a second temporary bonding adhesive (5) on a front surface of a second temporary carrier (4); 4) bonding a rear surface of the ultra-thin semiconductor wafer to the front surface of the second temporary carrier; 5) separating the ultra-thin semiconductor wafer from the first temporary carrier; 6) fabricating an integrated interconnection structure; 7) performing a bonding integration process; and 8) separating the integrated wafer from the second carrier. Two types of temporary bonding adhesives having different softening temperatures are used in conjunction with two temporary carriers, and a temporary bonding process and a bonding release process are used, thereby ensuring that the ultra-thin semiconductor wafer is supported by the temporary carrier during three-dimensional integration processes such as transferring, holding, interconnection structure fabrication, and bonding, and effectively reducing the risk of wafer cracking during the integration process.

The invention provides a semiconductor structure with a low resistance substrate and low power loss. The semiconductor structure comprises a semiconductor unit, a first conductive structure, a first conductive material and a second conductive structure, wherein the semiconductor unit is provided with a substrate, and the substrate is positioned at one side of the semiconductor unit and is provided with at least one hole; the first conductive material is positioned in the hole in a filling-in or underfilling way, and the first conductive structure is positioned on one surface of the side of the semiconductor unit; and the second conductive structure is positioned on the surface of the other side of the semiconductor unit different from the semiconductor substrate. The semiconductor structure can effectively reduce the resistance of the substrate, and further reduce the power loss during the breakover on the semiconductor structure, and also has a longer service life. In addition, without adding additional equipment, the advantages of the current packaging factory capacity can be continuously utilized, so that the power loss and potential die crack risks are further reduced.

The invention discloses a method for thinning a lithium niobate wafer, which belongs to the technical field of chip packaging. The thinning method of the lithium niobate wafer of the present invention comprises the following steps: providing a lithium niobate wafer, pasting the first dicing adhesive film on the back side of the lithium niobate wafer, and The dicing road is pre-cut to a predetermined depth; the first dicing film is removed, and a grinding film is attached to the front of the lithium niobate wafer, and the grinding film is a double-layer film; the back of the lithium niobate wafer is Grinding until the grains are separated; sticking a second dicing film on the back of the lithium niobate wafer, and then removing the grinding film. The invention realizes the cutting process of the lithium niobate wafer before grinding, and avoids the brittle failure, deep subsurface damage layer, and large cracking of the front and back sides of the cutting lithium niobate wafer in the prior art during grinding and cutting. Phenomenon, and the cracking of the front and back of the chip can be controlled within 10um, which is conducive to ensuring the quality of lithium niobate chip packaging products.

The present invention provides an LED manufacturing process, comprising providing a substrate, sequentially forming a buffer layer, a first semiconductor layer, a transition layer, a light-emitting layer, and a second semiconductor layer on the substrate; forming the first semiconductor layer During the process, the pressure of the reaction chamber is maintained at the first pressure, and during the process of forming the light-emitting layer, the pressure of the reaction chamber is maintained at the second pressure, and the second pressure is lower than the first pressure. During the formation of the transition layer, the pressure of the reaction chamber is The starting pressure of the body is equal to the first pressure, and the ending pressure is equal to the second pressure. In the present invention, by introducing a transition layer between the first semiconductor layer and the light-emitting layer, the continuous growth is maintained during the pressure change process at this stage, and the interfacial stress is reduced through the transition layer, so that the growth of the first semiconductor layer under high pressure conditions can be realized, and the growth rate can be increased. , due to the gradual reduction of pressure during the formation of the transition layer, the surface tensile stress of the first semiconductor layer gradually decreases, reducing the risk of cracks in the process.

The invention provides a cutting mechanism and method and a display panel. The cutting mechanism comprises a first output device and a second output device; the first output device drives a first cutting wheel to move along a first path to cut an array substrate of the display panel; the second output device drives a second cutting wheel to move along a second path to cut a color film substrate ofthe display panel; and in a first superposition section, the second path coincides with the first path to enable the first cutting wheel and the second cutting wheel to jointly cut sealing rubber onan edge between the array substrate and the color film substrate. The cutting mechanism and method and the display panel have the advantage that the display panel is prevented from breaking during piece split due to the fact that the sealing rubber is subjected to double-surface cutting or the sealing rubber is completely cut.

The present disclosure provides a droplet ejection device and related methods. The droplet ejection device comprises: a piezoelectric chip, an interdigital transducer arranged on the upper surface of the piezoelectric chip; the ratio of the thickness of the piezoelectric chip to the period of the interdigital transducer is 1 to 3 ; The interdigital transducer excites surface acoustic waves and bulk acoustic waves in the piezoelectric chip under the drive of radio frequency signals, and the surface acoustic waves and the bulk acoustic waves are reflected on the upper and lower surfaces of the piezoelectric chip to generate recombination Acoustic waves, to drive the liquid to be driven on the liquid attachment area to stretch along the direction perpendicular to the surface of the piezoelectric chip to form a liquid column, so that the liquid column will have a droplet pinch-off effect at the end, and a single droplet will be ejected; the liquid The attachment area is located on the upper surface and / or the lower surface of the piezoelectric chip corresponding to the area covered by the propagation of the surface acoustic wave generated by the interdigital transducer along the surface of the piezoelectric chip. It solves the problems of complicated device structure, high cost, low efficiency, and inconvenient realization of on-demand injection.

The invention discloses a solar cell and a photovoltaic module, the cell comprises a plurality of main grid lines and auxiliary grid lines, the plurality of main grid lines are arranged in parallel on the front surface of the cell and extend along the first direction of the cell; a plurality of auxiliary grid lines are arranged in parallel and are vertically intersected with the main grid lines; wherein the first distance between the main grid line arranged close to the first edge of the battery piece and the first edge is larger than or equal to 10 mm, and the first edge is the edge, extending in the first direction, of the battery piece. The solar cell provided by the embodiment of the invention can reduce the risk of layer fracture.

The application discloses a solar cell module and its preparation method, which belongs to the technical field of solar cells, and solves the problem of external force at the edge of the overlapping area of ​​the solar cell module in the prior art during the preparation process of the solar cell module and in the lamination process. It is prone to cracks or even slivers, and the problem of inconvenient processing. The preparation method of the present application includes the following steps: sequentially laying the first encapsulation film, the battery string, the second encapsulation film and the front cover on the rear cover to obtain a laminate; laminating the laminate to obtain a solar cell The assembly; the battery string includes a plurality of battery sheets connected in a head-to-tail overlapping manner; the first encapsulation film includes a main body and a plurality of local protrusions arranged on the main body and corresponding to the overlapping areas of the battery sheets, and / or Alternatively, the second encapsulation film includes a main body and a plurality of local protrusions disposed on the main body and corresponding to overlapping regions of the battery sheets. This application can be used for solar power generation.

The invention provides a solar cell and a preparation method thereof. A solar cell, characterized in that it comprises a flexible substrate (1); an adhesive layer (2) placed on the surface of the flexible substrate (1); a back metal layer (3) arranged on the surface of the adhesive layer (2) The battery material layer (4) that is arranged on the surface of the back metal layer (3); the front electrode layer (5) that is arranged on the surface of the battery material layer (4) at equal intervals; the cut-off layer ( that is arranged on the surface of the back metal layer (3) 6), and the cut-off layer (6) is adjacent to the battery material layer (4); the back electrode (7) embedded in the cut-off layer (6); the battery material layer ( 4) the surface, and the anti-reflection film layer (8) on the surface of the cut-off layer (6) other than the back electrode (7). The solar cell preparation method provided by the invention has low cost, high yield rate and high power-to-weight ratio.

The present application provides a bonding structure and a manufacturing method thereof. When bonding the nth wafer to the n-1th wafer, the first edge trimming can be performed from the bonding surface of the nth wafer. , the width of the first edge trimming is W n , as n increases, the first edge trimming width can gradually increase, this is because the edge of the wafer is usually not smooth enough, resulting in gaps in the wafer during bonding, after edge trimming of the wafer, The uneven part at the edge of the n-th wafer can be removed, and the bonding surface of the n-th wafer faces the bonding surface of the n-1-th wafer, and the n-th wafer and the n-1-th Wafer bonding, reducing the possibility of gaps between wafer bonding interfaces, improving the bonding strength between wafers, and then thinning the n-th wafer substrate to form the n-1th wafer stack , due to the stronger bonding strength between adjacent wafers, the resulting wafer stack has higher reliability and lower risk of splitting.

The invention discloses a method for preparing a heterogeneous semiconductor thin film, comprising: obtaining a semiconductor single crystal wafer with a first polished surface; obtaining a heterogeneous substrate with a second polished surface; After depositing a layer of buffer layer on the top to form the first composite structure; implanting barrier layer ions into the semiconductor single crystal wafer to form a barrier layer; annealing treatment; implanting H ions into the semiconductor single crystal wafer along the channel of the semiconductor single crystal wafer, the H ion The atomic number is smaller than the atomic number of the barrier layer ions, and the implantation energy is greater than the implantation energy of the barrier layer ions; the buffer layer is removed; the semiconductor single crystal wafer is bonded to the heterogeneous substrate to obtain the second composite structure; annealing treatment is obtained to obtain the heterogeneous semiconductor film. The invention forms a barrier layer in the semiconductor single crystal wafer by implanting barrier layer ions to trap H ions, thus reducing damage caused by ion stripping, thereby greatly improving the utilization rate of H ions and the quality of the film.