A modular multi-chip packaging structure and packaging method thereof

Abstract

The invention discloses a modular multi-chip packaging structure and a packaging method thereof. A plurality of packaging units are arrayed on a substrate, and the packaging unit is formed by a plurality of chips stacked in steps. The lead ends of the chips stacked in steps are located on the steps. On the surface, the lead ends of multiple chips are connected by chip wiring, and the chips do not need to be wired, which reduces the packaging volume of the chip and avoids the loss of electrical performance on the wirebond line. The plastic package is plastic-sealed. The bottom of the first plastic package is provided with an etched circuit connected to the chip wiring, and the connecting wiring is arranged on the substrate. The etched circuit at the bottom of the first plastic package is connected to the connection wiring on the substrate. Multiple packaging units are sealed on the substrate, and the chips are vertically placed on the substrate after plastic packaging. The independent modules can be packaged together to integrate different functions, which breaks the limitations of traditional multi-chip packaging, and has a simple structure. The connection is stable.

Description

【Technical field】 [0001] The invention belongs to the technical field of storage chip packaging, and in particular relates to a modular multi-chip packaging structure and a packaging method thereof. 【Background technique】 [0002] With the development of the semiconductor packaging industry, a multi-chip stacking technology has been used in the packaging of storage products to provide the package with a larger capacity for storing or executing data. The stacking method is superimposed to achieve expansion. The chips of each layer are directly interconnected through wire bond bonding. This method generally requires thinner chip thickness and the bonding wires are suspended, which is easy to cause chip cracks, and longer wire bond bonding is also There will be a loss of electrical performance. Therefore, for this packaging method, higher integration and reliability are crucial. 【Content of invention】 [0003] The object of the present invention is to overcome the disadvant...

AI Technical Summary

Problems solved by technology

[0002] With the development of the semiconductor packaging industry, a multi-chip stacking technology has been used in the packaging of storage products to provide the package with a larger capacity for storing or executing data. The stacking method is superimposed to achieve expansion. The chips of each layer are directly interconnected through wire bond bonding. This method generally requires thinner chip thickness and the bonding wires are suspended, which is easy to cause chip cracks, and longer wire bond bonding is also loss of electrical performance

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