73results about How to "Reduce particle pollution" patented technology

Methods and apparatus for reducing particle contamination on a reticle used in an extreme ultraviolet (EUV) lithography process. According to one aspect of the present invention, an apparatus that protects a surface of an object includes a plate that is positioned in proximity to the surface and protects at least a first portion of the surface. An opening is defined within the plate, and is such that a second portion of the surface is exposed through the opening. The apparatus also includes at least one magnetic component which creates a static magnetic field that is arranged to deflect charged particles away from the opening and the surface of the object.

Methods and apparatus for using a flow of a relatively cool gas to establish a temperature gradient between a reticle and a reticle shield to reduce particle contamination on the reticle are disclosed. According to one aspect of the present invention, an apparatus that reduces particle contamination on a surface of an object includes a plate and a gas supply. The plate is positioned in proximity to the object such that the plate, which has a second temperature, and the object, which has a first temperature, are substantially separated by a space. The gas supply supplies a gas flow into the space. The gas has a third temperature that is lower than both the first temperature and the second temperature. The gas cooperates with the plate and the object to create a temperature gradient and, hence, a thermophoretic force that conveys particles in the space away from the object.

A nonvolatile ferroelectric memory device includes a plurality of top array blocks disposed along a first direction, each having a plurality of top sub-cell array blocks disposed along a second direction perpendicular to the first direction, each of the top sub-cell array blocks include a first plurality of unit cells, a plurality of bottom array blocks disposed along the first direction below the plurality of top array blocks, each having a plurality of bottom sub-cell array blocks disposed along the second direction, each of the bottom sub-cell array blocks include a second plurality of unit cells, a plurality of sub-bit lines extending along the second direction and disposed at equal first intervals along the first direction, each sub-bit line connected to at least a first end of one of the first and second pluralities of unit cells, and a plurality of main bit lines extending along the second direction and disposed at the equal first intervals along a third direction perpendicular to both the first and second directions.

Methods and apparatus for using a flow of a relatively cool gas to establish a temperature gradient between a reticle and a reticle shield to reduce particle contamination on the reticle are disclosed. According to one aspect of the present invention, an apparatus that reduces particle contamination on a surface of an object includes a plate and a gas supply. The plate is positioned in proximity to the object such that the plate, which has a second temperature, and the object, which has a first temperature, are substantially separated by a space. The gas supply supplies a gas flow into the space. The gas has a third temperature that is lower than both the first temperature and the second temperature. The gas cooperates with the plate and the object to create a temperature gradient and, hence, a thermophoretic force that conveys particles in the space away from the object.

A method for singulating semiconductor wafers is disclosed. A preferred embodiment comprises forming scrub lines on one side of the wafer and filling the scrub lines with a temporary fill material. The wafer is then thinned by removing material from the opposite side of the wafer from the scrub lines, thereby exposing the temporary fill material on the opposite side. The temporary fill material is then removed, and the individual die are removed from the wafer.

A method and system is described for reducing particle contamination of a substrate in a deposition system. The deposition system comprises one or more particle diffusers disposed therein and configured to prevent or partially prevent the passage of film precursor particles, or break-up or partially break-up film precursor particles. The particle diffuser may be installed in the film precursor evaporation system, or the vapor delivery system, or the vapor distribution system, or two or more thereof.

The present invention is directed to aligning wafers within semiconductor fabrication tools. More particularly, one or more aspects of the present invention pertain to quickly and efficiently finding an alignment marking, such as an alignment notch, on a wafer to allow the wafer to be appropriately oriented within an alignment tool. Unlike conventional systems, the notch is located without firmly holding and spinning or rotating the wafer. Exposure to considerable backside contaminants is thereby mitigated and the complexity and / or cost associated with aligning the wafer is thereby reduced.

A system, method, and apparatus for mitigating contamination during ion implantation are provided. An ion source, end station, and mass analyzer positioned between the ion source and the end station are provided, wherein an ion beam is formed from the ion source and travels through the mass analyzer to the end station. An ion beam dump assembly comprising a particle collector, particle attractor, and shield are associated with the mass analyzer, wherein an electrical potential of the particle attractor is operable to attract and constrain contamination particles within the particle collector, and wherein the shield is operable to shield the electrical potential of the particle attractor from an electrical potential of an ion beam within the mass analyzer.

Disclosed is a die-bonding method having pick-and-probe features after wafer sawing where at least a die is probed and sorted according to different grades during a pick-and-place step performed after wafer sawing. A suction nozzle having a plurality of probes is utilized to probe the electrical terminals of the die. After picking, the suction nozzle is moved on a common moving path and the picked die is tested through the suction nozzle. The picked-and-probed die is moved and die-bonded to a die carrier loaded in a corresponding one of a plurality of die-bonding areas by moving the Suction nozzle on a chosen sorting path. Therefore, the die is probed and sorted during die-bonding processes. Higher graded dice at a same level are assembled on a same die carrier to form a higher graded semiconductor package.

A system for processing a workpiece includes a process head assembly and a base assembly. The process head assembly has a process head and an upper rotor. The base assembly has a base and a lower rotor. The base and lower rotor have magnets wherein the upper rotor is engageable with the lower rotor via a magnetic force created by the magnets. The engaged upper and lower rotors form a process chamber where a semiconductor wafer is positioned for processing. Process fluids for treating the workpiece are introduced into the process chamber, optionally while the processing head spins the workpiece. Additionally, air flow around and through the process chamber is managed to reduce particle adders on the workpiece.

Techniques for a door system for sealing an opening between two chambers in a semiconductor processing system are described. The opening has at least one angled corner. The door system includes a door, actuator, and sealing member. The door is moveable in the plane and has at least one angled corner to align the door with the opening. The actuator moves the door to selectively open and close the opening. The sealing member seals the opening when the door is in a closed position. The door is sized to apply substantially uniform seal compression to the sealing member when in the closed position.

The present invention is directed to aligning wafers within semiconductor fabrication tools. More particularly, one or more aspects of the present invention pertain to quickly and efficiently finding an alignment marking, such as an alignment notch, on a wafer to allow the wafer to be appropriately oriented within an alignment tool. Unlike conventional systems, the notch is located without firmly holding and spinning or rotating the wafer. Exposure to considerable backside contaminants is thereby mitigated and the complexity and / or cost associated with aligning the wafer is thereby reduced.

A method is disclosed for reducing particle contamination in an ion implantation system, wherein an ion beam is created via the ion source operating in conjunction with an extraction electrode assembly. A cathode voltage is applied to the ion source for generating ions therein, and a suppression voltage is applied to the extraction assembly for preventing electrons in the ion beam from being drawn into the ion source. The suppression voltage is selectively modulated, thereby inducing a current flow or an arc discharge through the extraction assembly to remove deposits on surfaces thereof to mitigate subsequent contamination of workpieces. An improvement to an ion implantation system is also disclosed in accordance with the foregoing, wherein a controller is configured to selectively modulate a voltage between a predetermined voltage and a predetermined suppression voltage generally concurrent with the transferring of the workpiece, thereby inducing a current flow or an arc discharge through the extraction electrode assembly to remove deposits on surfaces thereof to mitigate subsequent contamination of workpieces.

The present invention is directed to a beam control circuit and method used to minimize particle contamination in an ion implantation system by reducing the duty factor of the ion beam. In one embodiment the beam control circuit comprises a,high voltage switch connected in series with a power supply and an ion source portion of the ion implantation system, wherein the switch is operable to interrupt or reestablish a connection between the power supply and an electrode of the ion source including electrodes for plasma production. The beam control circuit also comprises a switch controller operable to control the duty factor of the ion beam by controlling the switch to close before a start of ion implantation and to open after a completion of implantation or at other times when the beam is not needed, thereby minimizing beam duty and particle contamination. The beam control technique may be applied to wafer doping implantation and duty factor reduction. Protection circuits for the high voltage switch absorb energy from reactive components and clamp any overvoltages.

The present invention is directed to a beam control circuit and method used to minimize particle contamination in an ion implantation system by reducing the duty factor of the ion beam. In one embodiment the beam control circuit comprises a high voltage switch connected in series with a power supply and an ion source portion of the ion implantation system, wherein the switch is operable to interrupt or reestablish a connection between the power supply and an electrode of the ion source including electrodes for plasma production. The beam control circuit also comprises a switch controller operable to control the duty factor of the ion beam by controlling the switch to close before a start of ion implantation and to open after a completion of implantation or at other times when the beam is not needed, thereby minimizing beam duty and particle contamination. The beam control technique may be applied to wafer doping implantation and duty factor reduction. Protection circuits for the high voltage switch absorb energy from reactive components and clamp any overvoltages.

A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick oxide on the wafer backside so that at least pre-selected oxide thickness remains after back end of line processing is complete and performing the back end of line processing of the memory device.

A ceramic sprayed member comprises a substrate and a ceramic sprayed coating thereon. Splats have been removed from the surface of the sprayed coating, typically by blasting. The ceramic sprayed member with improved plasma resistance mitigates particle contamination of wafers and enables stable manufacture when used in a halogen plasma process for semiconductor fabrication or the like.