56results about How to "Reduce cache size" patented technology

An apparatus, system, and method are disclosed for caching data. A storage request module detects an input/output (“I/O”) request for a storage device cached by solid-state storage media of a cache. A direct mapping module references a single mapping structure to determine that the cache comprises data of the I/O request. The single mapping structure maps each logical block address of the storage device directly to a logical block address of the cache. The single mapping structure maintains a fully associative relationship between logical block addresses of the storage device and physical storage addresses on the solid-state storage media. A cache fulfillment module satisfies the I/O request using the cache in response to the direct mapping module determining that the cache comprises at least one data block of the I/O request.

In preferred embodiments, a cryptographic device in which two key sets are stored: a normal key set (typically unique to the device) and a test key set (typically used by each of a relatively large number of devices). The device uses the normal key set in a normal operating mode and uses the test key set in at least one test mode which can be a built-in self test mode. Alternatively, the device stores test data (e.g., an intermediate result of an authentication exchange) in addition to or instead of the test key set. In other embodiments, the invention is a cryptographic device including a cache memory which caches a portion of a key set for performing an authentication exchange and/or at least one authentication value generated during an authentication exchange. Other embodiments of the invention are systems including devices that embody the invention and methods that can be performed by systems or devices that embody the invention.

This invention relates to a method (100) of operating a computing device to perform memoization. The method (100) includes determining whether or not a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) is characterised in that it includes transforming (104) by the computing device at least one selected from the group composed of the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship among and between the input parameters and output parameters of the function, the relationship reflecting redundancy.

A data processing apparatus generates a memory address corresponding to a first memory, and interpolates data read out from the first memory. The data processing apparatus selects a part of the memory address, checks if the first memory stores data corresponding to the selected part of the memory address, and transfers the data, for which it is determined that the first memory does not store the data, and which corresponds to the part of the memory address, from a second memory to the first memory. The data processing apparatus determines to change a part to be selected of the memory address based on the checking result indicating that the first memory does not store the data corresponding to the selected part of the memory address, and changes the part of the memory address corresponding to the characteristics of the memory address.

An improved caching method comprising: (a) employing circuitry to identify and analyze a plurality of data streams, each of said data streams resulting from a request to access a same content item stored in a cache; (b) calculating an initial access interval for said content item based upon said analyzing; and (c) adjusting a data transfer rate in at least one of said data streams in order to reduce said initial access interval to a reduced access interval.

Each sub-processor executes processing, assigned by a main processor, without reducing the performance of an entire system.

During transfer of data from the main memory to a cache, a sub-processor for performing decoding processing on a compressed image calculates a cache area based on a parameter indicating a feature of an image and adaptively changes a memory region to be cached, thereby increasing a cache hit probability during a subsequent processing. The performance of image signal processing performed by the sub-processor is improved, traffic in a system bus for memory transfer is reduced, and a decrease in the performance of the entire system is prevented.

The invention discloses a precise rate control method for intra-frame coding and relates to the technical field of digital image and video coding. The rate control method for intra-frame coding comprises the steps of: dividing a frame of images into block groups; describing complexity of the block groups by utilizing a sum of absolute values of gradients among adjacent pixel points in the block groups, and determining a quantization step of each block group by using an index model for a ratio of a coding data amount to the complexity. Therefore, rate control at the block group level is realized, and the purpose of precise control on the rate is realized.

The invention relates to the technical field of information and discloses a transmission method and system for a VOLTE video call. The method comprises the following steps that a receiving end receives a data package of the VOLTE video call and sends feedback information to a sending end, wherein the feedback information is a receiving state of the data package; the sending end judges whether packet loss exists according to the received feedback information; and if yes, the lost data package is retransmitted. Through the method, the sending end can check whether the packet loss exists, and when the packet loss exists, the reliable and quick data retransmission is realized, so that the overall delay and the system overhead are reduced.

The invention provides a capsule identification control method for a beverage machine. The beverage machine comprises a base, a brewing cup, a brewing head and an identification device, the brewing head and the identification device are both arranged on the base, a capsule is contained in the brewing cup, the brewing cup is rotatably matched with the brewing head, and the capsule comprises a diaphragm having an identification code. The capsule identification control method comprises a rotation identification step, wherein the brewing cup drives a capsule relative identification device to rotate, and the identification device detects the identification code on the diaphragm in real time and obtains identification data. According to the control method, in the rotation identification step, inthe process when the brewing cup is rotatably matched with the brewing head and the diaphragm is in a rotating state, the identification device detects the identification code and obtains the identification data. In the process of installing the brewing cup, the capsule identification process is completed, the identification efficiency is high, and the time for preparing a beverage is saved. In addition, the identification device and a brewing device are integrated, the structure is simple, the identification and brewing operation is continuous, and more convenience is provided for a user during use.

The invention discloses a TCP search optimization method under a high performance calculating network; the method comprises the following steps: 1, in TCP conversation processing, preferably calculating TCP conversations to obtain 32-bit short signatures if the TCP conversation order of magnitude is at the million level, carrying out XOR for the front 16-bit and rear 16-bit of the 32-bit short signatures obtained on the previous basis if the TCP conversation order of magnitude is at 100-million level, thus obtaining 16-bit short signatures; 2, respectively using the 32- bit short signatures and the 16-bit short signatures to replace a TCP tetrad identification TCP conversations; 3, building corresponding relations between the front P TCP conversation short signatures and Hash slots one by one; mapping the front P TCP conversation short signatures and Hash slots one by one if arrived TCP conversations exceed P, and assigning the TCP conversation short signatures (starting from P+1) from a TCB pool to a conflict list. The method can reduce the searching taken cache size, and can reduce the Hash conflict probability.

The invention proposes a low-latency ARINC 818 bus transceiving method. During the realization of mutual conversion between a VESA protocol and an ARINC 818 protocol according to the FPGA, the bufferamount of the data at a transmitting end can be reduced from the current frame to 1 line, and the buffer amount of the data at a receiving end can be reduced from the current frame to 40 lines due tothe optimization of a control algorithm, which greatly improves the real-time performance of video transmission. At the same time, resources required by the caching of a new algorithm can be satisfiedby the internal resources of the FPGA with no external memory needed, which reduces the difficulty of hardware design, reduces the resource overhead, and reduces the power consumption.

The embodiment of the invention relates to the technical field of communication and discloses an approach and system for implementing message tracking. The approach includes the first step that a subsystem which a first track point belongs to obtains to-be-tracked messages from a subsystem which a second track point belongs to and serial number information of the second track point; the second step that the to-be-tracked messages and serial number information of the first track point are sent to a subsystem which a third track point belongs to; the third step that the serial number information of the second track point is added to the to-be-tracked messages and is cached; the fourth step that a response message fed back by a subsystem which a track stop point of a track chain belongs to is received; the fifth step that whether the cached to-be-tracked messages need persistence is judged, and if yes, the cached to-be-tracked messages are uploaded to a network management subsystem; the sixth step that the network management subsystem analyzes at least two uploaded and cached messages and obtains a track trace of the to-be-tracked messages. Through the adoption of the approach, the cached track messages of the network management subsystem can be reduced, consumption of system resources can be reduced, and fault location speed can be improved.