301results about How to "Enhance the shake effect" patented technology

A circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit. At least one additional inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, which may distributed throughout the integrated circuit, has an inductance value selected to resonate with impedance of the capacitive clock distribution circuit. By operating the clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

A charge pump circuit includes a charge pump having an output voltage. A replica circuit actively matches up and down currents in the charge pump. A charge pump bias current transistor biases the charge pump. The charge pump includes four switches driven by differential UP and DOWN signals. The charge pump includes a first tail current source connected between a supply voltage and two of the four switches that are driven by the differential UP signal, and a second tail current source connected between a supply voltage and two of the four switches that are driven by the differential DOWN signal. The charge pump includes an operational amplifier whose output is connected to an output of one of the tail current sources. A dump capacitor is connected to a negative input of the operational amplifier. The replica circuit includes four transistors, two of which match the first and second tail current sources, and the other two match the switches driven by the differential UP and DOWN signals. The replica circuit includes a second operational amplifier that matches the charge up and down current for varied output voltage. A low pass filter is at the output voltage and includes a resistor-capacitor network.

An instantaneous phase error detector (IPED) and method includes a first gate configured to logically OR output phase error signals as data to a first latch, and a second gate configured to logically combine the output phase error signals to clock the first latch. A delay element delays to the data to the first latch where the output of the first latch provides instantaneous phase error change information. A second latch is coupled to the output phase error signals to output a lead / lag signal to indicate which of the output phase error signals is leading. A phase-locked loop employing the output of the IPED is also disclosed along with static phase measurement and jitter optimization features.

A circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit. By operating the clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

The invention relates to a configurable phase discriminator for a time-delay locking ring, which comprises a configurable SRAM, an integral resetting module, an advanced-lagged signal generating module and a fine adjusting range identification signal generating module. Data in the embedded configurable SRAM is changed and different phase discriminating precisions are set according to different application requirements, so as to realize the controllability of fine and rough adjusting; meanwhile, as the embedded configurable SRAM controls different starting moments of fine adjusting, the structure of hardware does not need to be changed in the using process and the locking time of a loop circuit can be adjusted only by changing a code stream in the SRAM according to the requirements. In addition, the advanced-lagged signal generating module which is composed of two D triggers and three RS triggers is used for sampling and outputting two input clock signals and judging whether the two input clock signals are advanced or lagged; the fine adjusting range identification signal generating module which is composed of a nand gate and two pulse generating circuits is used not only for judging whether the phase difference of the two clocks reaches the set fine adjusting range, but also for controlling the starting time of fine adjusting by controlling the pulse generating width.

A novel propellant management device used in a propellant storage box comprises a central supporting column, flow guide blades, supporting column blades, large blades, liquid storage blades, an upper pressing plate, an upper mesh, an upper supporting plate, small cylinders, a framework, a lower pressing plate, a lower mesh and a lower supporting plate, wherein the flow guide blades, the supporting column blades and the large blades are all fixedly mounted on the central supporting column in the radial direction to form an integral structure, the integral structure is fixedly mounted on the upper pressing plate through the central supporting column, the supporting column blades and the large blades are mounted in the same plane, and a mounting plane of each flow guide blade and a mounting plane of each large blade form a certain included angle; the liquid storage blades are fixedly mounted on the upper pressing plate in the radial direction; the upper pressing plate, the upper mesh, the upper supporting plate, the small cylinders, the middle framework, the lower pressing plate, the lower mesh and the lower supporting plate are sequentially fixedly mounted from top to bottom to form the integral structure, namely, a liquid accumulation assembly. The novel propellant management device has the inhibition function on shaking of liquid, performs comprehensive management on propellants and is simple in structure, high in strength and reliability and large in liquid storage capacity, the on-orbit work application range is large, the on-orbit liquid discharge speed is high, and meanwhile, repeated large-flow filling on the ground can be realized.

The present invention provides a data rate controller system for determining the coder used, and hence the data rate, for a plurality of channels in an associated network. Each channel provides statistical information about an associated signal to a central controller (or call / resource manager). The controller considers the information and sends control instructions to each channel for selecting an appropriate coder and / or data rate. The statistical information might include lost-frame rate, jitter, call event discrimination, and system resource utilization. By considering each channel from a centralized standpoint, the network can be optimized according to network capabilities and channel resource capabilities. A profile might also be used where each channel autonomously chooses a coder based upon background noise derived from the source signal.

A phase-locked loop (PLL) circuit includes a power-on-reset (POR) to reset a digital block and set an initial input voltage value VCTRL of voltage-controlled oscillator (VCO). An input divider and a feedback divider are provided to set the frequency ratio of output to input and to raise the resolution of the output frequency. First and second phase frequency detectors are used to measure the phase difference between the two input signals and generate a pulse corresponding to the phase difference. First and second reducing dividers are inserted before the first and second phase frequency detectors to decrease the input frequency of the respective phase frequency detector and keep the ratio of the input frequency and natural frequency (Wn) as a constant. A lock-state detector is used to detect whether the PLL is locked or unlocked. A charge pump is used to provide charge signals corresponding to the pulse. A loop filter is coupled to the output node of the charge pump to provide a voltage VCTRL responding to the charge signals.

The invention discloses a vein blood sample shaking up device for a clinical laboratory of a hospital. The vein blood sample shaking up device comprises a base, a guide rod, a screw rod, a hoisting block, an arc-shaped clamping claw, a shaking up platform, a rectangular translation frame, a driving motor, an incomplete gear and a fixed sleeve ring, and is characterized in that the hoisting block is mounted on the screw rod through a thread; a clamping force arm is fixedly mounted at the right end of a shaft sleeve through a connecting rod; gears are arranged at front and rear sides in the rectangular translation frame; the gears in the rectangular translation frame are adaptive to a gear on the incomplete gear; the fixed sleeve ring is fixedly connected to the rear side of the rectangular translation frame trough a connecting rod. According to the vein blood sample shaking up device disclosed by the invention, a test tube is indirectly driven by manually rotating a shaking up wheel to move downward into the fixed sleeve ring, so that the shaking up of blood collection tubes with different lengths is met and the commonality of the shaking up device is improved; the incomplete gear is matched with the rectangular translation frame so that the fixed sleeve ring moves leftward and rightward and the blood collection tubes are driven to swing leftward and rightward, and furthermore, the shaking up effect of vein blood is improved.

The invention discloses an anti-shake type camera support for the animation major. According to the anti-shake type camera support, a telescopic driving piece, a damping adjusting piece and a lockingcomponent are arranged in an angle support component, wherein the damping adjusting piece can adjust the damping of the telescopic driving piece; the larger the damping, the better the anti-shape effect is during the adjusting process; and after the adjustment, the locking component is adopted for locking to avoid the following shaking problem and improve the shooting stability. A stability augmentation platform can greatly lower the gravity center of the camera support to improve the stability and reduce the shaking performance when the camera is moved; a spring anti-shake component can counteract shake through the counterforce generated by the spring, can effectively respond to the shake problem caused by the camera support and ensures the shooting quality; the camera support does not slide during the using process to facilitate stability; and in addition, the camera support is high in practicality and convenient to carry.

The invention discloses a ring oscillator. The ring oscillator mainly comprises three differential delay units D1, D2 and D3 connected in series and an injection unit INJ. 180-degree phase shift is realized from the input end of the first delay unit to the output end of the third serial-connection delay unit, the delay time is reduced through feedback of multiple loops, and the oscillation frequency is further improved. Each differential delay unit is provided with a rough tuning circuit and a fine tuning circuit, wherein the rough tuning circuit is used for setting the minimum delay or the maximum delay, and the fine tuning unit is used for adjusting the minimum delay and the maximum delay. Subharmonic signals at the frequency of output signals are injected to a grid electrode of the injection unit, and the shaking performance of the oscillator is improved. The ring oscillator has the rough tuning and fine tuning functions within the wide-frequency range, is low in voltage sensitivity, reduces the influences of bias voltage fluctuation, realizes low-shaking output clock signals and can be applied to a wireless receiver frequency synthesizer or a clock data recovery circuit.

A sampling device (2) comprising a first input port (4) and a second input port (5), wherein an input-signal is fed to the first input port (4) and wherein an optical clock signal is fed to the second input port (5). The sampling device (2) comprises a plurality of track and hold units (7 1 , 7 2 , 7 N ), wherein each of the plurality of track and hold units (7 1 , 7 2 , 7 N ) is connected to the first input port (4). The plurality of the track and hold units (7 1 , 7 2 , 7 N ) is further connected to the second input port (5) through an optical waveguide (11) in such a manner that the plurality of tack and hold units (7 1 , 7 2 , 7 N ) operate in a time-interleaved mode.

A field-programmable gate array (“FPGA”) may include data receiver and / or transmitter circuitry that is adapted to receive and / or transmit data at any frequency(ies) or data rate(s) in a wide range of possible frequencies or data rates. Phase-locked loop (PLL) circuitry may be needed for operation of such receiver and / or transmitter circuitry. For satisfactory operation over the wide frequency range, multiple PLL circuits are provided. One of these PLL circuits may be capable of operating over the entire frequency range, possibly with better jitter performance in some portions of the range than in other portions of the range. One or more other PLL circuits may be provided that are focused on particular parts of the broad range, especially where the jitter performance of the first-mentioned PLL may not be adequate to meet some possible needs.

The invention discloses a clock data recovery circuit with a waveform screening function for a PAM4 receiver and the PAM4 receiver. The clock data recovery circuit for the PAM4 receiver comprises a clock data recovery circuit body with a comparator module and a phase discriminator module, wherein the front end of the phase discriminator module is connected with a waveform screening circuit in series, and the waveform screening circuit is used for selecting symmetrical waveforms in output signals of the comparator module as an output; the PAM4 receiver comprises the clock data recovery circuitfor the PAM4 receiver. The objective of the invention is to solve the problem that the CDR of a PAM4 receiver deteriorates the jitter performance of a recovery clock while improving the phase discrimination density. According to the invention, the waveform screening circuit is added, and the waveform screening circuit selects symmetrical jump edges in the output signals of the three comparators asthe input of the phase discriminator, thereby improving the phase discrimination precision while improving the phase discrimination density, and improving the jitter performance of a CDR recovery clock while guaranteeing the quick locking of a loop.

The present invention provides an oscillation circuit comprising: a plurality of multi-stage inverter rings, each of which has an odd number of inverters connected in cascade with each other to form the ring through an equally odd number of nodes on the ring; a group of inverters , for connecting each node on any given one multi-level inverter ring to a corresponding one on another multi-level inverter ring in order to shift the phases of the generated oscillating signals relative to each other by a fixed difference, in order to combine this particular and other multi-stage inverter rings with each other; and a current source connected to the inverters of the multi-stage inverter ring and the inverters of the inverter group.