61 results about "Storage class memory" patented technology

A buffer manager that manages blocks of memory amongst multiple levels of buffer pools. For instance, there may be a first level buffer pool for blocks in first level memory, and a second level buffer pool for blocks in second level memory. The first level buffer pool evicts blocks to the second level buffer pool if the blocks are not used above a first threshold level. The second level buffer pool evicts blocks to a yet lower level if they have not used above a second threshold level. The first level memory may be dynamic random access memory, whereas the second level memory may be storage class memory, such as a solid state disk. By using such a storage class memory, the working block set of the buffer manager may be increased without resorting to lower efficiency random block access from yet lower level memory such as disk.

A method and a storage system are provided for implementing enhanced solid-state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing dynamic random access memory (DRAM), and at least one non-volatile memory, for example, Phase Change memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

The present invention provides a memory data quick persistence method based on a storage-class memory. The method is based on a flat mixed memory architecture, and is implemented by collaborative design of a user layer and a kernel layer. The method comprises: abstracting an SCM with a certain capacity and data stored in the SCM into a persistent area; designing an application programming interface (API) at the user layer, and making a response to memory access of an application to the persistent area; extending a Buddy system of a kernel to implement heterogeneous mixed memory management; and designing a persistent area manager to implement the functions of persistent mapping in the persistent area, metadata management in the persistent area and the like. According to the memory data quick persistence method based on the storage-class memory, a data linearization process required for data persistence in a traditional storage architecture can be avoided, direct access and in-place update of persistent data can be implemented, hierarchy invoking of a software stack in the traditional architecture is simplified, the I/O bottleneck can be effectively alleviated, and the memory access performance of the persistent data can be improved.

A Computerized storage system management methods and system configurations. In some embodiments the invention comprises a computer storage data access structure, a DS management and a storage system solution related to methods and a system geared for implementing a scale-out NAS that can effectively utilize client side Flashes while the Flash utilization solution is based on pNFS, the pNFS is comprised of a meta-data server (MDS) and data servers (DSs). There are at least one client and two Data servers, wherein at least one of them is a Direct Attached (Tier0), client level DS. Tier0 DS is a client-side resident low latency memory selected from a group of solid state memories, defined as Storage Class Memories, such as a Flash memory, serving as an integral lowest level of a storage system with a shared storage hierarchy of levels (Tier 0, 1, 2 and so on) and the unified name space.

Embodiments of the present invention provide a system, method and computer program products for memory space management for storage class memory. One embodiment comprises a method for information storage in an information technology environment. The method comprises storing data in a storage class memory (SCM) space, and storing storage management metadata corresponding to said data, in the SCM in a first data structure. The method further includes buffering storage management metadata corresponding to said data, in a main memory in a second data structure.

The invention provides an SCM (Storage Class Memory)-based Key-Value log-type local-storage method. The storage method comprises the following steps: an SCM dividing step, wherein partition dividing is carried out on an SCM according to functions, that is, the SCM is divided into five different logic partitions of a superblock area, a checkpoint area, a page management area, a static-hash-table area and a data storage area; a multilayer memory management step, wherein three layers of memory management modules are built, the memory is managed at different layers, and dynamic allocation and reclaimation of pages are realized; and a high-concurrency hash-table building step, wherein a static hash table is used to index key-value objects, and a dynamically allocated array is used to store hash-conflicting elements. According to the method realized in the invention, storage space is reasonably scheduled and allocated according to hardware characteristics of a heterogeneous memory medium, autilization rate of the storage medium is increased, service life of hardware is prolonged, and concurrency and data throughput of a hybrid key-value storage system are improved.

The embodiment of the invention provides a KV (Key Value) storage method and device, and relates to the field of data storage. The method comprises the following steps that: when a target KV is stored, storing a Value in the target KV into a variable-length page in an SCM (Storage Class Memory); updating a primary index and a mapping table, wherein the primary index comprises a mapping relationship between a Key and a logic address in the stored KV, and the mapping table comprises a mapping relationship between the logic address and the physical address of the stored KV; when a first combination condition is met, combining the Value in the variable-length page to a fixed-length page in the SCM; updating the mapping table; when a second combination condition is met, combining the Value in the fixed-length page to a block page in an SSD (Solid State Drive); and updating the mapping table again. By use of the method, the problem of low performance of KV storage in the prior art is solved, and an effect on improving KV storage performance can be achieved.

An area for prefetching is determined while accommodating an increase in a block address space. A prediction model predicts prefetch addresses for each of bit ranges into which block addresses are split by using a plurality of neural networks assuming charge of the different bit ranges having performed machine learning on I/O trace data, a prediction accuracy determination section determines a size of an area for prefetching on the basis of addresses in the bit range for which prediction accuracy in prefetch is lower than a predetermined value, a predicted value determination section determines addresses of the area for prefetching on the basis of addresses in the bit range for which the prediction accuracy in the prefetch is equal to or higher than the predetermined value, and a prefetch issuance section caches data in the area for prefetching in a storage class memory from a NAND flash memory.

Emerging byte-addressable persistent memory technologies, generically referred to as Storage Class Memory, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Unifying storage and memory into a memory tier that can be accessed directly requires additional burden to ensure that groups of memory operations to persistent or nonvolatile memory locations are performed sequentially, atomically, and not caught in the cache hierarchy.

The present invention provides a lightweight solution for the atomicity and durability of write operations to nonvolatile memory, while simultaneously supporting fast paths through the cache hierarchy to memory. The invention includes a hardware-supported solution with modifications to the memory hierarchy comprising a victim cache and additional memory controller logic. The invention also includes a software only method and system that provides atomic persistence to nonvolatile memory using a software alias in DRAM and log in nonvolatile memory.

The embodiment of the invention provides a data transmission method, device and system, relates to the field of computers, can lower memory bus bandwidth occupied by data transmission and improves the use efficiency of the memory bus bandwidth. The method comprises the following steps: the data transmission device receives data sent from other hosts; the data transmission device writes the data into a SCM (Storage Class Memory) through a memory controller according to the address of the SCM; and after the data transmission device receives data writing finishing response fed back from the SCM, the data transmission device sends a data processing instruction to a CPU (Central Processing Unit), and the CPU is used for indicating the memory controller to write data in a cache into the SCM according to the data processing instruction. The method is used for data transmission.

Staging data record changes from a faster storage medium to a slower storage medium using data query rewriting is provided. In response to receiving a data query corresponding to a particular data record, it is determined whether the data query is one of a transactional data query or an analytical data query. In response to determining that the data query is a transactional data query, the transactional data query is rewritten to apply transactional delta changes to the particular data record on a storage-class memory of a computer. In response to determining that the data query is an analytical data query, the analytical data query is rewritten to select and reconcile each data record corresponding to the particular data record stored on the storage-class memory with the particular data record stored on a persistent data storage device of the computer.