117 results about "Quantum wire" patented technology

In a semiconductor device, concave sections in which an opening area becomes small in proportion as a depth becomes deep are formed in a crystal layer, and a quantum structure is formed on at least one crystal face of a bottom section of the concave section and a border formed between plural sidewalls thereof. In case the quantum structure is formed in the bottom section, a quantum box is formed therein. If the quantum structure is formed in the border between the sidewalls of the concave section, a quantum wire is formed therein. In case the quantum structure is formed in the sidewall of the concave section, a two-dimensional quantum well is formed therein.

A programmable dopant fiber includes a plurality of quantum structures formed on a fiber-shaped substrate, wherein the substrate includes one or more energy-carrying control paths (34), possibly surrounded by an insulator (35), which pass energy to quantum structures. Quantum structures may include quantum dot particles (37) on the surface of the fiber or electrodes (30) on top of barrier layers (31) and transport layer (32) which form quantum dot devices (QD). The energy passing through the control paths (34) drives charge carriers into the quantum dots (QD), leading to the formation of “artificial atoms” with real-time tunable properties. These artificial atoms then serve as programmable dopants, which alter the behavior of surrounding materials. The fiber can be used as a programmable dopant inside bulk materials, as a building block for new materials with unique properties, or as a substitute for quantum dots or quantum wires in certain applications.

The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.

A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.

A method of making semiconductor quantum wires employs a semiconductor wafer (14) as starting material. The wafer (14) is weakly doped p type with a shallow heavily doped p layer therein for current flow uniformity purposes. The wafer (14) is anodised in 20% aqueous hydrofluoric acid to produce a layer (5) microns thick with 70% porosity and good crystallinity. The layer is subsequently etched in concentrated hydrofluoric acid, which provides a slow etch rate. The etch increases porosity to a level in the region of 80% or above. At such a level, pores overlap and isolated quantum wires are expected to form with diameters less than or equal to 3 nm. The etched layer exhibits photoluminescence emission at photon energies well above the silicon bandgap (1.1 eV) and extending into the red region (1.6-2.0 eV) of the visible spectrum.

This invention concerns the fabrication of nanoscale and atomic scale devices. The method involves creating one or more registration markers. Using a SEM or optical microscope to form an image of the registration markers and the tip of a scanning tunnelling microscope (STM). Using the image to position and reposition the STM tip to pattern the device structure. Forming the active region of the device and then encapsulating it such that one or more of the registration markers are still visible to allow correct positioning of surface electrodes. The method can be used to form any number of device structures including quantum wires, single electron transistors, arrays or gate regions. The method can also be used to produce 3D devices by patterning subsequent layers with the STM and encapsulating in between.

A semiconductor light-emitting device fabricated in the (Al,Ga,In)N materials system has an active region for light emission (3) comprising InGaN quantum dots or InGaN quantum wires. An AlGaN layer (6) is provided on a substrate side of the active region. This increases the optical output of the light-emitting device. This increased optical output is believed to result from the AlxGa1-xN layer serving, in use, to promote the injection of carriers into the active region.

A negative resistance field-effect element that is a negative differential resistance field-effect element capable of achieving negative resistance at a low power supply voltage (low drain voltage) and also enabling securement of a high PVCR is formed on its InP substrate 11 having an asymmetrical V-groove whose surface on one side is a (100) plane and surface on the other side is a (011) plane with an InAlAs barrier layer (12) that has a trench (TR) one of whose opposed lateral faces is a (111) A plane and the other of which is a (331) B plane. An InGaAs quantum wire (13) that has a relatively narrow energy band gap is formed at the trench bottom surface as a high-mobility channel. An InAlAs modulation-doped layer (20) having a relatively wide energy band gap is formed on the quantum wire as a low-mobility channel. A source electrode (42) and a drain electrode (43) each in electrical continuity with the quantum wire (13) constituting the high-mobility channel through a contact layer (30) and extending in the longitudinal direction of the quantum wire (13) as spaced from each other, and a gate electrode (41) provided between the source electrode (42) and the drain electrode (43) to face the low-mobility channel (20) through an insulating layer or a Schottky junction, are provided. Owing to the foregoing configuration, a very narrow-width quantum wire whose lateral confinement size can, without restriction by the lithographic technology limit, be made 100 nm or less is usable as a high-mobility channel, whereby there can be obtained a negative resistance field-effect element that develops a negative characteristic at a low power supply voltage and enables securement of a high PVCR.

A new fabrication method for nanovoids-imbedded bismuth telluride (Bi—Te) material with low dimensional (quantum-dots, quantum-wires, or quantum-wells) structure was conceived during the development of advanced thermoelectric (TE) materials. Bismuth telluride is currently the best-known candidate material for solid-state TE cooling devices because it possesses the highest TE figure of merit at room temperature. The innovative process described here allows nanometer-scale voids to be incorporated in Bi—Te material. The final nanovoid structure such as void size, size distribution, void location, etc. can be also controlled under various process conditions.

A microelectronic device provided with one or more quantum wires, able to form one or more transistor channels, and optimized in terms of arrangement, shape, and / or composition. A method for fabricating the device includes forming, in one or more thin layers resting on a support, a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, forming a structure connecting the first block to the second block, and forming, on the surface of the structure, wires connecting a first region of the first block with another region of the second block that faces the first region.