1847 results about "Path system" patented technology

Systems and methods for identifying pixels that are inside a two-dimensional path may be used to fill the path. The path is segmented and a point in space is identified that is used to generate a triangle fan, where each triangle in the fan is formed by one of the segments of the path and the point. Locations in a winding buffer are updated for each pixel that is within a triangle of the triangle fan. The resulting winding buffer indicates the pixels that are inside the two-dimensional path. The winding buffer may be used to fill the path.

In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

An optical signal return path system includes a transmitter having a sample clock generator for generating a sample clock and an RF signal receiver for receiving and converting an analog RF data signal into a first data stream of digitized RF data samples at a rate determined by the sample clock. Supplemental channel circuitry provides a second data stream. A multiplexor receives and combines the first data stream and second data stream, and an optical transmitter converting the combined data stream into a serialized optical data signal for transmission over an optical fiber. The second data stream may contain maintenance data reflecting an operational state of the transmitter. A receiver receives the optical data signal and recovers therefrom a digital data stream and an associated first clock having an associated first clock rate. The data stream is stored in a memory device at the first clock rate. A clock generator generates a second clock having an associated second clock rate that is adjusted in accordance with a clock control signal. A control circuit reads data from the memory device at a rate corresponding to the second clock rate and generates a fullness signal that indicates whether the memory device is more full than a predefined threshold fullness level. A clock speed adjusting circuit generates the clock control signal in accordance with the fullness signal.