654results about How to "Reduce voltage drop" patented technology

A method for forming optical devices includes providing a gallium nitride substrate having a crystalline surface region and a backside region. The backside is subjected to a laser scribing process to form scribe regions. Metal contacts overly the scribe regions.

A leadframe for use in an integrated circuit package is described. The leadframe comprises a plurality of electrically conductive leads, a die attach pad, and an electrically conductive ring or rings formed generally around the circumference of the die attach pad and between the die attach pad and leads. In one embodiment, at least one of the leads is formed integrally with each ring. The die attach pad may also be formed integrally with one or more leads. In another embodiment, the ring or rings are formed so that they are electrically isolated from the die attach pad, and the die attach pad, leads, and ring or rings are all formed in substantially the same plane. In some embodiments, the ring or rings are broken into electrically isolated sections. Each of the ring sections (and die attach pad, if appropriate) may be electrically connected to a voltage source outside the integrated circuit package (e.g., a power supply or ground). The leadframe is formed from a single sheet of material by, for instance, stamping or etching. The leadframe may be used in either ceramic or plastic packages. The leadframe reduces switching noise and crosstalk, allows more flexibility in placement of power and/or ground bond pads on the die, and allows provision of ground and power planes in an integrated circuit package that is thinner than previous integrated circuit packages containing both ground and power planes.

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device

An active matrix color crystal display has an active matrix circuit, a counterelectrode panel and an interposed layer of liquid crystal. The active matrix display is located in a portable microdisplay system. The image is written to the the display therein causing the liquid crystal to move to a specific image position. A light source is flashed to illuminate the display. The pixel electrodes are set to a specific value to cause the liquid crystal to move towards a desired position. The process of writing, flashing, and setting the electrode intensity value to reorient the liquid crystal to produce an image is repeated. Portable system can include a digital camera, cellular telephone, camcorder, heads up display, instant print camera, pager,

The organic electroluminescence display apparatus of the present invention comprises a first and second substrates, the former being coated with banks for separating pixels, a lower electrode, organic light-emitting layer and upper electrode of a transparent material in this order, and the latter being coated with a color filter and electroconductive shadow pattern, wherein the organic light-emitting layer surrounded by the banks for separating pixels faces the color filter, and the first and second substrates face each other in such a way that the upper electrode over the banks for separating pixels is electrically connected to the electroconductive shadow pattern. This structure connects at least one of the upper electrode and electroconductive shadow pattern to a power supply point, to control ununiform emitted light brightness which may result from voltage drop at the upper transparent electrode. Moreover, the organic light-emitting layer can be formed without a vapor deposition mask having a precise aperture pattern, to efficiently produce the organic EL display apparatus.

An organic light-emitting display device which is transparent by improving a transmittance in transmitting regions and which reduces a voltage drop in an opposite electrode comprises: a substrate having a transmitting region and pixel regions separated from each other by the transmitting region; thin film transistors positioned on the substrate and disposed in the pixel regions, respectively; a passivation layer covering the thin film transistors, formed in the transmitting region and the pixel regions, and having a first opening formed in a location corresponding to at least a portion of the transmitting region; pixel electrodes formed on the passivation layer so as to be electrically connected to the thin film transistors, respectively, located in the pixel regions, and disposed so as to overlap and cover the thin film transistors, respectively; an opposite electrode facing the pixel electrodes, formed so as to be able to transmit light, and located in the transmitting region and the pixel regions; an organic emission layer interposed between the pixel electrodes and the opposite electrode so as to emit light; and a conduction unit formed of a conductive material, disposed so as to overlap with the first opening, and contacting the opposite electrode.

Aspects of the present disclosure provide an integrated circuit (IC) test structure. An IC structure according to the present disclosure can include: a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level; a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.

A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters.

It is an object of the present invention to suppress an influence of voltage drop due to wiring resistance to make an image quality of a display device uniform. In addition, it is also an object of the present invention to suppress delay due to a wiring for electrically connecting a driving circuit portion to an input/output terminal to improve an operation speed in the driving circuit portion.

In the present invention, a wiring including copper for realizing lowered wiring resistance, subjected to microfabrication, is used as a wiring used for a semiconductor device and a barrier conductive film for preventing diffusion of copper is provided for a TFT as a part of the wiring including copper to form the wiring including copper without diffusion of copper into a semiconductor layer of the TFT. The wiring including copper is a wiring including a laminate film of at least a conductive film containing copper as its main component, subjected to microfabricaiton, and the barrier conductive film.

The present invention is directed to a linear connector assembly comprising a plug connector (22) and a receptacle connector (24). The plug connector (22) includes an elongated member (26), and an electrical contact (72) disposed about a portion of the elongated member. The receptacle connector (24) includes a wall defining a cavity (44) dimensioned to sealingly receive the elongated member, and an electrical contact having a surface disposed in the wall for electrical connection with the plug contact. The electrical contacts of the plug connector (22) and the receptacle connector (24) have spherical surface portions whereby a spherical interlace between the electrical contacts is formed upon make-up and reduces voltage drops between the contacts.

Disclosed is a low-cost hybrid storage solution that allows Code like sector-alterable NOR and Data like block-alterable NAND and byte-alterable EEPROM being integrated on a same die. The disclosed combo NVM design of the present invention is a truly Data-oriented NVM design that allows 2T-EEPROM to integrate both 0.5T-NAND and 1T-NOR without sacrificing any EEPROM's byte-write performance in the same die. The invention provides several new embodiment sets of preferable bias conditions of Program, Program-Inhibit, Erase and Erase-Inhibit for operating bit-write, byte-write, sector-write and page-write for several preferable Flotox-based EEPROM, NOR and NAND or combo NVM arrays that include types of shared SL, 8-pair BLs and SLS, with or without GBL, normally Erased Vt and Programmed Vt, or the reversed Erased-Vt or Programmed-Vt, etc. Further disclosed is a flexible X-decoder design to allow the flexible selection of pages to be erased to save erase time. Also disclosed is using on-chip negative voltage for FT's gate along with the less positive HV applied to FTs' channel region for same write performance but with the benefits of channel length reduction in cell and less BVDS electric requirement in peripheral devices for more scalable manufacturing process.

A charging pad 10 is provided with a power supply coil 11, and a device housing a battery 50 containing an induction coil 51. A device housing a battery 50 is provided with a rectifying circuit 53 that rectifies AC power induced in the induction coil 51, a charging circuit 54 that charges the internal battery 52 with output from the rectifying circuit 53, a shorting circuit 56 that short circuits the terminals of the induction coil 51, and a control circuit 57 that controls the shorting circuit 56 ON when a charging abnormality is detected. If the control circuit 57 detects a charging abnormality during power transmission from the charging pad 10 power supply coil 11 to the device housing a battery 50 induction coil 51, it controls the shorting circuit 56 ON to cut-off the supply of power from the induction coil 51 to the rectifying circuit 53.