78 results about "Gate count" patented technology

A synchronous network traffic processor that synchronously processes, analyzes and generates data for high-speed network protocols, on a wire-speed, word-by-word basis. The synchronous network processor is protocol independent and may be programmed to convert protocols on the fly. An embodiment of the synchronous network processor described has a low gate count and can be easily implemented using programmable logic. An appropriately programmed synchronous network traffic processor may replace modules traditionally implemented with hard-wired logic or ASIC.

A low density One-Time Programmable (OTP) memory is disclosed to achieve low gate count and low overhead in the peripheral circuits to save the cost. A maximum-length Linear Feedback Shift Register (LFSR) can be used to generate 2n−1 address spaces from an n-bit address. The registers used in the address generator can have two latches. Each latch has two cross-coupled inverters with two outputs coupled to the drains of two MOS input devices, respectively. The inputs of the latch are coupled to the gates of the MOS input devices, respectively. The sources of the MOS input devices are coupled to the drains of at least one MOS device(s), whose gate(s) are coupled to a clock signal and whose source(s) are coupled to a supply voltage. The two latches can be constructed in serial with the outputs of the first latch coupled to the inputs of the second latch.

The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing data transfer between the two clock domains at one data item per cycle of the lower of the two frequencies. Depending on the frequency difference between the data producer and consumer, the initial latency could be as low as a fraction of a cycle and no more than two cycles of the consumer's clock. The operation of the data transfer FIFO circuit has been verified using gate-level simulations for several ratios of clock frequencies.

An authentication system and a method for signing data are disclosed. The system uses a hardware software partitioned approach. In its implementation the system of the invention compares favourably with performance and other parameters with a complete hardware or full software implementation. Particularly, advantageously there is a reduced gate count. Also as disclosed in the invention the system makes it difficult for hackers to attack the system using simple power analysis.

The invention provides a baseband system for a short-range radio communication system. The baseband system complies with the Bluetooth baseband specification and is well suited for efficient hardware implementation, providing low power, small size and low cost radio subsystem design. The baseband system includes a transceiver unit and a buffer unit so that the system has an efficient gate count and reduced power consumption. The transceiver unit design is based on pipelined signal processing with distributed datapath flow control. The transceiver unit processes outgoing and incoming packets and comprises several signal processing units connected in series so that each signal processing unit is clocked by a common clock signal. A mode line is connected to each signal processing unit for switching each signal processing unit between transmit mode and receive mode. Control lines connected to each signal processing unit convey flow control information to one or more preceding signal processing units in transmit mode, or to one or more subsequent signal processing units in receive mode. The buffer unit comprises a buffer system applying a flexible memory management concept that results in an efficient implementation of buffers or storage elements in terms of gate count and power consumption and provides the ability to dynamically allocate memory for variable length user packets flexibility. The buffer system holding the data of the first processing unit and the second processing unit comprises several storage elements such that each storage element has a first storage unit and a second storage unit. A switching subsystem is provided for switching the individual storage elements between the first and second modes. In the first mode, each first storage unit is addressable by a first processing unit and each second storage unit is addressable by a second processing unit. In the second mode, each second storage unit is addressable by the first processing unit, and each first storage unit is addressable by the second processing unit.