329 results about "Doping profile" patented technology

Disclosed herein are methods of doping a patterned substrate in a reaction chamber. The methods may include forming a first conformal film layer which has a dopant source including a dopant, and driving some of the dopant into the substrate to form a conformal doping profile. In some embodiments, forming the first film layer may include introducing a dopant precursor into the reaction chamber, adsorbing the dopant precursor under conditions whereby it forms an adsorption-limited layer, and reacting the adsorbed dopant precursor to form the dopant source. Also disclosed herein are apparatuses for doping a substrate which may include a reaction chamber, a gas inlet, and a controller having machine readable code including instructions for operating the gas inlet to introduce dopant precursor into the reaction chamber so that it is adsorbed, and instructions for reacting the adsorbed dopant precursor to form a film layer containing a dopant source.

The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source / drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.

A novel semiconductor transistor is presented. The semiconductor structure has a MOSFET like structure, with the difference that the device channel is formed in an intrinsic region, so as to effectively decrease the impurity and surface scattering phenomena deriving from a high doping profile typical of conventional MOS devices. Due to the presence of the un-doped channel region, the proposed structure greatly reduces Random Doping Fluctuation (RDF) phenomena decreasing the threshold voltage variation between different devices. In order to control the threshold voltage of the device, a heavily doped poly-silicon or metallic gate is used. However, differently from standard CMOS devices, a high work-function metallic material, or a heavily p-doped poly-silicon layer, is used for a n-channel device and a low work-function metallic material, or heavily n-doped poly-silicon layer, is used for a p-channel FET.

A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode. Indium is implanted to form halo implants adjacent to the LDD regions and underlying the gate electrode wherein the halo implants extend to an interface between the epitaxial silicon layer and the carbon-doped silicon layer wherein carbon ions in the carbon-doped silicon layer act as a silicon interstitial sink for silicon interstitials formed by the halo implants to prevent end of range secondary defect formation.

A high-voltage transistor includes first and second trenches that define a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members being separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

High speed optical modulators can be made of a lateral PN diode formed in a silicon optical rib waveguide, disposed on a SOI or other silicon based substrate. A PN junction is formed at the boundary of the P and N doped regions. The depletion region at the PN junction overlaps with the center of a guided optical mode propagating through the waveguide. Electrically modulating a lateral PN diode causes a phase shift in an optical wave propagating through the waveguide. Each of the doped regions can have a stepped or gradient doping profile within it or several doped sections with different doping concentrations. Forming the doped regions of a PN diode modulator with stepped or gradient doping profiles can optimize the trade off between the series resistance of the PN diode and the optical loss in the center of the waveguide due to the presence of dopants.

An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.

A method in which thin-film p-i-n heterojunction photodiodes are formed by selective epitaxial growth / deposition on pre-designated active-area regions of standard CMOS devices. The thin-film p-i-n photodiodes are formed on active areas (for example n+-doped), and these are contacted at the bottom (substrate) side by the “well contact” corresponding to that particular active area. There is no actual potential well since that particular active area has only one type of doping. The top of each photodiode has a separate contact formed thereon. The selective epitaxial growth of the p-i-n photodiodes is modular, in the sense that there is no need to change any of the steps developed for the “pure” CMOS process flow. Since the active region is epitaxially deposited, there is the possibility of forming sharp doping profiles and band-gap engineering during the epitaxial process, thereby optimizing several device parameters for higher performance. This new type of light sensor architecture, monolithically integrated with CMOS, decouples the photo-absorption active region from the MOSFETs, hence the bias applied to the photodiode can be independent from the bias between the source, drain, gate and substrate (well) of the MOSFETs.

A method for fabricating a back-illuminated semiconductor imaging device on a thin semiconductor-on-insulator substrate, and resulting imaging device. Resulting device has a monotonically varying doping profile which provides a desired electric field and eliminates a dead band proximate to the backside surface.

In system for implanting workpieces with an accurately parallel scanned ion beam, a fine-control collimator construct is used to reduce the deviation of the scanned ion beam from a specified axis of parallelism and thereby improve its collimation. The shape of the fine-control collimator matches the ribbon shape of the beam and correction of parallelism in two orthogonal directions is possible. Measurement of the non-parallelism is accomplished by sampling the scanned beam in two planes and comparing timing information; and such measurement is calibrated to the orientation of the workpiece in the plane where ion implantation occurs. Measurement of non-uniformity in the doping profile is accomplished using the same means; and the scan waveform is adjusted to substantially remove any non-uniformity in the doping profile.