124 results about "Binade" patented technology

Binarization a data value comprises binarizing the minimum of the data value and a predetermined cut-off value in accordance with a first binarization scheme, in order to yield a primary prefix. If the data value is greater than the cut-off value, binarizing a difference of the data value minus the predetermined cut-off value in accordance with a second binarization scheme to obtain a binary suffix, the first binarization scheme being different from the second binarization scheme, and appending the primary suffix to the primary prefix is performed. A very effective compression of data values may be achieve by using the binarization scheme for preparing the syntax elements for the arithmetic coding, the binarization schemes substantially being a combination of two different binarization schemes, and by using binary arithmetic coding instead of m-ary arithmetic coding for coding the binarized syntax elements.

The purpose of this invention is to provide a method / system which can prevent the conflict of the software. The base is compartmentalized to the first floor to the M floor, M>= 1.The talked method includes: (a) prescan the square function which the binary system of the executable code transfers and the transfer or transferred square function which are belong to the case of the first floor. If the value of M is larger than 1, it also prescans the transfer square function which belongs to the first floor to the M-1floor and the transferred square function which are belong to the second floor from the M floor. (b)If there is at least one conflict, then at least information of the conflict can be saved, and (c) when the process transfers the direct base, if there is corresponding conflict information, it will give up loading the base, or loading the base.

An optimization technique for optimizing binary codes in a language having access to a zoned decimal type variable and applicable to binary codes including instructions which can cause side effects. The optimization technique includes: detecting, for each variable, an area including access to a zoned decimal type variable and not including an instruction that can cause a side effect, from the binary codes read into a memory; and performing, in the detected area, a process for converting a zoned decimal type variable to a binary type variable, a process for deleting such a pack / unpack code that a converted result does not change even in case the pack / unpack code is deleted, from the binary codes, or a process for performing combination of the processes.

The invention belongs to the technical field of computers, and particularly relates to a multi-level hybrid vulnerability automatic mining method, which comprises the following steps: S1, obtaining pointer distribution and assignment processes in a program by utilizing pointer analysis through a static analysis technology, and recording memory address positions pointed by all pointers; obtaining adestination operand of the CMP type instruction by using an alias analysis technology so as to clarify a jump address of the target program; and S2, realizing instrumentation of the monitoring code to the key position of the target program through an intermediate code static instrumentation technology. According to the invention, the binary executable program is translated into the middle-layer representation language of the compiler, and compared with the binary executable program, the middle-layer representation language source code obtained through processing of the method has more semantic information; compared with C / C + + language analysis, the static analysis technology for the LLVM IR intermediate representation language can realize finer-grained static semantic information extraction during compiling.

The invention provides a method and device for realizing cross-platform multi-language development, a medium and electronic equipment. The method comprises the steps of obtaining a first mixed code set; analyzing the first mixed code set to obtain a first fragment code corresponding to each programming language; analyzing all first fragment codes corresponding to the programming language based onthe grammatical analysis model of each programming language, and generating a first abstract syntax tree corresponding to the programming language; utilizing the cross-platform framework compiler of each programming language to compile a first abstract syntax tree corresponding to the programming language, and generating a core binary file corresponding to the programming language; wherein the core binary file can run in a virtual machine of a cross-platform framework.

A method and apparatus of entropy coding of coding symbols using Context-Based Adaptive Binary Arithmetic Coder (CABAC) are disclosed. According to the present invention, a math formula is used for calculating the LPS range for deriving rangeOne value and rangeZero value. For example, the LPS range is derived using one or more mathematical operations comprising calculating a multiplication of a first value and a second value, in which the first value is related to (2*the LPS probability index+1) or the LPS probability index, while the second value is related to (2*the range index+1) or the range index. Besides, the LPS range can be derived by using a look-up-table including table contents corresponding to values of LPS range associated with a set of LPS probability indexes and a set of range indexes for encoding or decoding a binary value of the current bin.

A source binary code that complies with a source architecture is translated to a target binary code that complies with a target architecture. The target binary code includes a first target portion translated from a respective source portion of the source binary code. During execution of the target binary code on a processor that complies with a target architecture, it is determined whether to retranslate the source portion to produce a second target portion that is more optimized to the target architecture than the first target portion or to retranslate the source portion to produce a third target portion that is more optimized to the target architecture than the second target portion.

The invention proposes a method of protection of a Boolean circuit associated with a structural description of the circuit comprising elementary Boolean variables, each represented by one bit, the method comprising the steps consisting in:selecting a set of k elementary Boolean variables of the circuit as a function of predefined selection criteria,constructing a variable x represented by k bits by concatenation of the k selected variables in accordance with a chosen order,determining a binary code C comprising a set of code words and belonging to a given vector space and the supplementary code D of said binary code C as a function of a condition bearing on the dual distance of said supplementary code D, said binary code C having a length n and a size 2k, where k designates the number of bits representing said variable x;substituting the variable x in the structural description of the Boolean circuit with a protected variable z represented by n bits so that:any operation of writing on the variable x in the circuit is substituted with an operation of writing on the variable z, the variable z being generated by adding the variable x encoded by said code C to a random bit vector y encoded by the supplementary code D, andany operation of reading the variable x in the circuit is substituted with an operation of reading the value of the protected variable z and an operation of decoding said read value of the protected variable z using a decoding matrix J of size (n×k) determined from the binary code C and the supplementary code D of the binary code C.

The provided adaptive arithmetic code method comprises: A. making received binary bit bin as current bin; B. with initial probability space of current bin, calculating probability space of the bin before normalization, and executing step C and D paralleled; C. taking the first normalization process for probability space of current bin as the initial space of next bin, back to step A; and D. taking second normalization process for probability space of current bin, and outputting bit code flow. This invention improves coding efficiency.

Compressing program binaries with reduced compression ratios. One or several pre-processing acts are performed before performing compression using a local sequential correlation oriented compression technology such as PPM, or one of its variants or improvements. One pre-processing act splits the binaries into several substreams that have high local sequential correlation. Such splitting takes into consideration the correlation between common fields in different instructions as well as the correlation between different fields in the same instruction. Another pre-processing reschedules binary instructions to improve the degree of local sequential correlation without affecting dependencies between instructions. Yet another pre-processing act replaces common operation codes in the instruction with a symbols from a second alphabet, thereby distinguishing between operation codes that have a particular value, and other portions of the instruction that just happen to have the same value. Local sequential correlation compression such as PPM is then performed.

A method for optimizing binary code in a language having access to binary coded decimal variable. The method includes: generating a first compiler expression of the binary code; analyzing a use-definition and / or a definition-use for the first compiler expression; generating a second compiler expression by identifying logical binary coded decimal (BCD) variables in the first compiler expression; assigning temporary variables to the logical BCD variables, wherein the second compiler expression includes packed decimal operations and the assigned temporary variables; and converting a packed decimal operation in the second compiler expression and an assigned temporary variable to a decimal floating point (DFP) if sign information and precision information are not lost during conversion from BCD to DFP, wherein identifying logical BCD variables includes: in the use-definition and / or definition-use of operands, regarding an operand of definition and an operand of use as the same logical BCD variables.

A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

The invention discloses a matching rule engine supporting a combined expression of multivariate protocol variables, and relates to the technical field of information. The matching rule engine is composed of a rule definition device, a lexical parser, a grammar parser, a compiler and a binary code generator. The rule definition device is composed of a rule input device, a rule detection engine anda rule output device. According to the matching rule engine, an extended Berkeley packet filtering technology is improved, so that rule grammar of the matching rule engine can be customized, and function nesting calling, function variable reference, cache range offset and nesting expression evaluation are supported. According to the matching rule engine, the JIT technology is adopted, dynamic compilation is carried out into machine code operation, the execution efficiency can be comparable to that of a C program, and good system portability is achieved.

Methods and apparatus with floating point processing are provided. A method includes receiving a first floating point operand and a second floating point operand, each having an n-bit format comprising a sign field, an exponent field, and a significand field, normalizing a binary value obtained by performing arithmetic operations for fields corresponding to each other in the first and second floating point operands for an n-bit multiplication operation, determining whether the normalized binary value is a number that is representable in the n-bit format or an extended normal number that is not representable in the n-bit format, according to a result of the determining, encoding the normalized binary value using an extension bit format in which an extension pin identifying whether the normalized binary value is the extended normal number is added to the n-bit format, and outputting the encoded binary value using the extended bit format, as a result of the n-bit multiplication operation.

Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations.

A method, system and article of manufacture for generating binary query results and, more particularly, for generating a binary result set from non-binary data. One embodiment comprises receiving a request for a binary result set for an object containing result fields, and operating on the object to generate the binary result set from non-binary result data associated with the result fields. Operating on the object comprises accessing at least one field definition for at least one of the result fields to retrieve one or more value constraints that define allowable values for the at least one result field. Using the one or more retrieved value constraints, the non-binary result data associated with the result fields is rendered in a binary format, whereby the binary result set is generated.