1594results about How to "Scale up" patented technology

The present invention describes methods and processes for the production of proteins, particularly glycoproteins, by animal cell or mammalian cell culture, illustratively, but not limited to, fed-batch cell cultures. The methods comprise feeding the cells with D-galactose, preferably with feed medium containing D-galactose, preferably daily, to sustain a sialylation effective level of D-galactose in the culture for its duration, thus increasing sialylation of the produced proteins. The methods can also comprise at least two temperature shifts performed during the culturing period, in which the temperature is lower at the end of the culturing period than at the time of initial cell culture. The cell culture processes of the invention involving two or more temperature shifts sustain a high cell viability, and can allow for an extended protein production phase. The methods can also comprise the delayed addition of polyanionic compound at a time after innoculation. Supplementation of the cultures with D-galactose, preferably in a feed medium, to sustain galactose at sialylation effective levels in the cultures until the end of a culture run reverses a decline in sialylation that accompanies culture scale up, and is advantageous for large scale culturing processes.

The present invention provides a flash memory element and its manufacturing method having improved overall memory characteristics by constituting a double-gate element for improving the scaling down characteristic of flash memory element. With the above double-gate flash memory structure, a flash memory element in the present invention improves the scaling down characteristic and the programming and retention characteristic of a flash memory element.

A spread spectrum transmitter provides delays having different magnitudes to spread spectrum (SS) signals for a plurality of channels, and multiplexes the SS signals to generate transmission multiplex SS signal. A spread spectrum receiver calculates a partial correlation value between the transmission multiplex SS signal and spreading codes multiplied to the SS signals, multiplies the partial correlation values by a prescribed matrix prepared based on each orthogonal code sequence to calculate a plurality of orthogonal correlation values. The receiver identifies for a respective channel each parallel data sequence related in advance to an orthogonal code sequence whose orthogonal correlation value is a maximum, corrects delay differences of the parallel data sequences, and then performs sampling and parallel-serial conversion to obtain a serial demodulated data sequence.

A method includes determining a distance between an eye and a device, and adjusting a scale of content displayed on the device based on the distance.

The conventional flash memory device is fabricated by the MOS processing technology on a bulk substrate and has a similar configuration to an MOS device.While the conventional CMOS device has a superior scaling down characteristic, the scaling down characteristic of a flash memory device is poor due to the inability to reduce the thickness below 7 nm or 8 nm for the tunneling oxide film where the charges in the channel are tunneled into the floating electrode through the tunneling oxide.In order to resolve this problem, the present invention, instead of a SOI wafer, uses a cheaper bulk silicon wafer with lower defect density. A wall shape Fin active region where the channel and the source / drain are formed is connected to the bulk silicon substrate by which floating body effect and heat conduction problem are resolved. a flash memory device is fabricated by forming a tunneling oxide film on side surfaces of the Fin active and a floating (storage) electrode where the charges could be stored.The above structure has a superior scaling down characteristic and enhanced memory performance due to a double-gate flash memory device structure.