37results about How to "Reduce time skew" patented technology

A sheet processing apparatus includes a hole punching section arranged downstream from a skew detecting unit and orthogonally to a conveying path of a sheet, and a control unit configured to change the tilt angle of the hole punching section in accordance with each of the quantity of skew at the forward edge and the quantity of skew at the rear edge of the sheet, carry out skew correction at the forward edge within a first correction range w1, and carry out skew correction at the rear edge within a second correction range w2 (where w1>w2≧w1 / 2). The control unit carries out skew correction at the forward edge within the correction range w2, in the case where the detected quantity of skew at the forward edge is a tilt angle exceeding the correction range w2, and then carries out skew correction at the rear edge in accordance with the difference between the quantity of skew at the forward edge after the correction and the quantity of skew at the rear edge.

The invention discloses a method for adopting high-accuracy pulse per second frequency multiplication to produce sampling pulses based on an FPGA in the technical field of electric power system measurement and control and aims at solving the technical problem that sampling pulses provided by an oscillator in the prior art enable the sampling accuracy to be low. In the method, an actual synchronous pulse per second counting value is compared with an ideal synchronous pulse per second counting value, deviations and sampling frequencies are subjected to accumulation calculation, the correction situation of a pulse counter is judged according to an accumulation calculation result, accordingly total deviations of actual synchronous pulses per second are averagely distributed in actual sampling pulses, sampling pulse errors are remarkably decreased, and reliable and stable sampling pulse signals are provided for analog-digital signal acquisition. In addition, the method is simple and easy to operate, occupied FPGA chip resources are decreased, and the running speed and reliability of the FPGA are improved.

Reducing timing skew begins with identifying signals that are to have a reduced timing skew. These identified signals are then routed to reduce the layout distance of each signal path. Among these identified signals, a longest signal path is found and the signal paths of the remaining identified signals are lengthened. The lengthening is done to each of the remaining identified signal paths to each have a length substantially equal to the longest signal path whereby the timing skew between the identified signals is reduced. A signal length matching process may be stored as a program in a computer-readable medium with the program operable on a computer system tailored for providing chip placement and routing processes.

A differential signal pair transmission structure adapted to a wiring board and including a first signal path and a second signal path is provided. The first signal path includes a first upper trace, a first lower trace and a first conductive through via. The second signal path includes a second upper trace, a second lower trace and a second conductive through via. A portion of the first signal path and a portion of the second signal path overlaps in the normal projection onto the upper or lower surface of the wiring board. Normal projections of the first and the second signal path projecting onto the upper surface of the wiring board are substantially symmetric with respect to a line which is perpendicular to a segment connecting normal projections of axes of the first and the second through via onto the upper surface and passes through the midpoint of the segment.

A pin electronics circuit for automatic test equipment includes first and second sampling circuits for sampling first and second legs of a differential signal produced by a DUT (Device Under Test). Timing signals activate the first and second sampling circuits to sample the legs of the differential signal at precisely defined instants of time to produce first and second collections of samples. To deskew the legs of a differential signal with respect to each other, corresponding features within the first and second collections are identified and a difference is taken between them. The differential skew can then be applied to correct measurements of differential signals.

The invention provides a method and a system for switching main and standby synchronous clocks under a BC (Basic Control) mode of a PTN (Packet Transport Network) synchronous network of a wide area protection system. Wide area control protection devices of various substations are connected through a PTN network device and interstation time synchronization is realized by adopting a BC synchronizing function of a transmission IEEE1588V2 protocol; when the main synchronous clock has a fault, a time service interface of each wide area control protection device is cut off, and the standby synchronous clock is fast tracked in this time; and after time precision of the standby synchronous clock is determined, switching completion information is sent to all PTN network devices to realize time service of each wide area control protection device again. The method and the system have the characteristics of fast fault switching speed, high accuracy, good signal transmission quality and low time deviation ratio of each wide area control protection device in a fault process of the synchronous clock.

A multi-block SRAM memory system is described where a single global clock pulse is distributed to each memory block from the central control. At each SRAM memory block a local signal generator uses the globally distributed clock pulse to generate the required memory control pulse signals. By generating the memory control pulses locally, instead of distributing these from the central control the variations in skew are greatly reduced. Thus the required timing relationship between memory control signals can be achieved with smaller timing margins. This allows higher speed memory cycle and more reliable memory operation.

In a system and method for feature alignment in chromatographic systems, the system runs a first sample through a first separation column. The system determines a first set of features for the first sample run. The system runs a second sample through a second separation column and detects a second set of features for the second sample run. The system estimates a systematic shift in features between the first sample run through the first separation column and the second sample run through the second separation column. The system adjusts the second set of features detected for the second sample run through the second separation column based on the estimated systematic shift to obtain a third set of adjusted features.

A DDR2 SDRAM memory module having memory chips arranged bilaterally symmetrical on the module. A register chip is arranged on each of two faces of the memory module, with each register chip coupled to half of the memory chips.

Reducing timing skew begins with identifying signals that are to have a reduced timing skew. These identified signals are then routed to reduce the layout distance of each signal path. Among these identified signals, a longest signal path is found and the signal paths of the remaining identified signals are lengthened. The lengthening is done to each of the remaining identified signal paths to each have a length substantially equal to the longest signal path whereby the timing skew between the identified signals is reduced. A signal length matching process may be stored as a program in a computer-readable medium with the program operable on a computer system tailored for providing chip placement and routing processes.

Disclosed are a circuit and method for acquiring and updating a transparent clock. The circuit includes an MII interface monitoring module, an arrival timestamp recording module, a timer, an MAC layerprocessing module, a departure timestamp recording module, a transparent clock calculating module, a transparent clock updating module, an arrival timestamp table, and a configuration parameter table. Clock synchronization is one of key technologies in time-triggered Ethernet. The clock synchronization is to maintain the synchronization of clocks of distributed equipment, and the transparent clock technology is one of methods to achieve the clock synchronization. The invention provides a circuit realization method for acquiring and updating the transparent clock. The circuit and method have advantages of being able to quickly acquire a precise transparent clock and timely modify a transparent clock value in a synchronization message, and can provide a basic guarantee for high precision clock synchronization.

Disclosed herein is a scan optimizer system and method designed to generate optimal ATE input / output timing with small margin but yielding stable results. Therefore the scan test time is greatly improved.

The invention discloses a method for adopting high-accuracy pulse per second frequency multiplication to produce sampling pulses based on an FPGA in the technical field of electric power system measurement and control and aims at solving the technical problem that sampling pulses provided by an oscillator in the prior art enable the sampling accuracy to be low. In the method, an actual synchronous pulse per second counting value is compared with an ideal synchronous pulse per second counting value, deviations and sampling frequencies are subjected to accumulation calculation, the correction situation of a pulse counter is judged according to an accumulation calculation result, accordingly total deviations of actual synchronous pulses per second are averagely distributed in actual sampling pulses, sampling pulse errors are remarkably decreased, and reliable and stable sampling pulse signals are provided for analog-digital signal acquisition. In addition, the method is simple and easy to operate, occupied FPGA chip resources are decreased, and the running speed and reliability of the FPGA are improved.

The invention discloses a time synchronization method, server and system. The method comprises the following steps that: a time server receives frequency information sent by a ground centralized clock source; and the time server calculates time according to the frequency information and the initial time, and sends the time information to a downstream base station. Through the method, the server and the system, the defect of low reliability of time synchronization in the prior art can be solved, and time synchronization still can be realized when a satellite is failed for a long time.

The invention discloses a satellite communication terminal digital clock synchronization method and device; the method comprises the following steps: calculating frequency difference between a masterstation clock and a terminal digital clock according to time information continuously sent by a master station within a set time interval; calculating a frequency adjustment value by utilizing a frequency adjustment algorithm according to the frequency difference, and controlling the output frequency of the digital clock of the terminal according to the frequency adjustment value so as to achievefrequency synchronization with the master station clock; adding the obtained latest master station clock and set link delay to obtain master station time and loading the time to local time so as to realize time synchronization of the local time and the main station clock; the device comprises a main station time obtaining module, an adjusting control module, a digital frequency conversion module and a loading control module. According to the method and the device, the convergence rate, the precision and the robustness of time synchronization are greatly improved, the structure is simple and easy to be implemented, and the purpose of synchronization of the main station clock and the local clock can be rapidly achieved.