The invention provides a built-in self-
test structure of an on-
chip embedded Flash. The structure comprises a custom control module, an FBIST controller, an ERASE module and a BYPASS module. After being enabled, the FBIST controller initiates operation; according to mutual matching between an internal controller state
machine and the custom control module and between the internal controller state
machine and the ERASE module, address and reading / writing sequence operation and erasure switching are realized; a readout result and an on-
chip comparator are subjected to test result comparison; a result representation
signal is output; when a test is ended, a test completion mark jumps; internal access of the FLASH and test result comparison are realized; only a test starting
signal and a controller
clock signal are required externally; after the test is ended, a test result is represented with a test completion flag bit and a
test failure flag bit; a failure address, an
algorithm execution state, a reading / writing state and output
data information of the FLASH can be mastered, so that a basis is provided for further fault locating; and the built-in self-test of the
chip-level or
system-level embedded FLASH is realized.